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    Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of material
    12.
    发明授权
    Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of material 有权
    具有接触结构的半导体器件和位于形成在材料层中的沟槽中的栅极结构

    公开(公告)号：US09299781B2

    公开(公告)日：2016-03-29

    申请号：US14242416

    申请日：2014-04-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  William J. Taylor, Jr. ,  Ryan Ryoung-Han Kim

    IPC: H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

    CPC classification number: H01L29/0847 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851

    Abstract: One illustrative device disclosed herein includes, among other things, an active region defined in a semiconductor substrate, a layer of material positioned above the substrate, a plurality of laterally spaced-apart source/drain trenches formed in the layer of material above the active region, a conductive source/drain contact structure formed within each of the source/drain trenches, a gate trench formed at least partially in the layer of material between the spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure.

    Abstract translation: 本文公开的一个说明性器件尤其包括限定在半导体衬底中的有源区，位于衬底上方的材料层，形成在有源区上方的材料层中的多个横向间隔开的源极/漏极沟槽 形成在每个源极/漏极沟槽内的导电源极/漏极接触结构，至少部分地形成在材料层中的间隔开的源极/漏极沟槽之间的材料层中的栅极沟槽，其中层的部分 的材料保持位于源极/漏极沟槽和栅极沟槽之间，位于栅极沟槽内的栅极结构以及位于栅极结构之上的栅极盖层。

    Methods of forming stressed fin channel structures for FinFET semiconductor devices
    13.
    发明授权
    Methods of forming stressed fin channel structures for FinFET semiconductor devices 有权
    形成用于FinFET半导体器件的应力鳍式通道结构的方法

    公开(公告)号：US08889500B1

    公开(公告)日：2014-11-18

    申请号：US13960244

    申请日：2013-08-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, Jr.

    IPC: H01L21/338 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/785

    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of fin-formation trenches that define a fin, forming a first stressed layer within the trenches and above the fin and performing at least one etching process on the first stressed layer so as to define spaced-apart portions of the first stressed layer positioned at least partially within the trenches on opposite sides of the fin. The method also includes forming spaced-apart portions of a second stressed layer above the spaced-apart portions of the first layer, forming a third stressed layer above the fin between the spaced-apart portions of the second layer and, after forming the third layer, forming a conductive layer above the second and third layers.

    Abstract translation: 本文公开的一种说明性方法包括形成限定翅片的多个翅片形成沟槽，在沟槽内和翅片上方形成第一应力层，并在第一应力层上执行至少一个蚀刻工艺，以便 以限定至少部分地位于鳍片的相对侧上的沟槽内的第一应力层的间隔开的部分。 该方法还包括在第一层的间隔开的部分上方形成第二应力层的间隔开的部分，在第二层间隔开的部分之间形成翅片之上的第三应力层，在形成第三层之后 在第二层和第三层上形成导电层。

    Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device
    14.
    发明授权
    Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device 有权
    用双应力通道形成三维半导体器件的方法和所得到的器件

    公开(公告)号：US08877588B2

    公开(公告)日：2014-11-04

    申请号：US13764115

    申请日：2013-02-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Daniel T. Pham ,  Werner Juengling ,  William J. Taylor, Jr. ,  Robert Miller

    IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/66795 ,  H01L29/7846 ,  H01L29/785

    Abstract: One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different than the first type of stress, and forming a gate structure around a portion of the fin structure. One device includes first and second spaced-apart trenches in a semiconducting substrate defining at least a portion of a fin for the device, a stress-inducing material having a first type of stress in the first trench, a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different type than the first stress, and a gate structure around a portion of the fin structure.

    Abstract translation: 一种方法包括形成第一和第二间隔开的沟槽，其至少部分延伸到限定用于器件的鳍结构的半导体衬底中，形成在第一沟槽中具有第一类型应力的应力诱导材料，形成第二应力诱导 第二沟槽中的材料，第二应力诱导材料具有不同于第一类型应力的第二应力，以及围绕鳍结构的一部分形成栅极结构。 一个器件包括在半导体衬底中限定用于器件的鳍片的至少一部分的第一和第二间隔开的沟槽，在第一沟槽中具有第一类型应力的应力诱导材料，在第一沟槽中的第二应力诱导材料 第二沟槽，第二应力诱导材料具有与第一应力不同的第二应力，以及围绕鳍结构的一部分的栅极结构。

    Methods of forming contact structures for semiconductor devices and the resulting devices
    16.
    发明授权
    Methods of forming contact structures for semiconductor devices and the resulting devices 有权
    形成用于半导体器件和所得器件的接触结构的方法

    公开(公告)号：US09330972B2

    公开(公告)日：2016-05-03

    申请号：US14457708

    申请日：2014-08-12

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Vimal Kamineni ,  William J. Taylor, Jr.

    IPC: H01L27/12 ,  H01L21/84 ,  H01L21/425 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/535

    CPC classification number: H01L29/4975 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/535 ,  H01L29/41758 ,  H01L29/78 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One method disclosed herein includes, among other things, a method of forming a contact structure to a source/drain region of a transistor device. The transistor device includes a gate structure and a gate cap layer positioned above the gate structure. The method includes forming an extended-height epi contact structure that is conductively coupled to the source/drain region. The extended-height epi contact structure includes an upper surface that is positioned at a height level that is above a height level of an upper surface of the gate cap layer. The method further includes performing an etching process to trim at least a lateral width of a portion of the extended-height epi contact structure, and, after performing the etching process, forming a metal silicide material on at least a portion of the trimmed extended-height epi contact structure and forming a conductive contact on the metal silicide material.

    Abstract translation: 本文公开的一种方法包括形成与晶体管器件的源极/漏极区域的接触结构的方法。 晶体管器件包括栅极结构和位于栅极结构上方的栅极帽层。 该方法包括形成导电耦合到源极/漏极区的扩展高度外延接触结构。 所述延伸高度外延接触结构包括位于所述栅极盖层的上表面的高度以上的高度水平处的上表面。 该方法还包括执行蚀刻工艺以修剪延伸高度外延接触结构的一部分的至少横向宽度，并且在执行蚀刻工艺之后，在修剪的延伸高度外延接触结构的至少一部分上形成金属硅化物材料， 高度epi接触结构，并在金属硅化物材料上形成导电接触。

    Forming gate and source/drain contact openings by performing a common etch patterning process
    17.
    发明授权
    Forming gate and source/drain contact openings by performing a common etch patterning process 有权
    通过执行公共蚀刻图案化工艺来形成栅极和源极/漏极接触开口

    公开(公告)号：US09312182B2

    公开(公告)日：2016-04-12

    申请号：US14301748

    申请日：2014-06-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  William J. Taylor, Jr. ,  Min Gyu Sung

    IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/06

    CPC classification number: H01L29/41783 ,  H01L21/28008 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/0653

    Abstract: One method disclosed herein includes forming an opening in a layer of material so as to expose the source/drain regions of a transistor and a first portion of a gate cap layer positioned above an active region, reducing the thickness of a portion of the gate cap layer positioned above the isolation region, defining separate initial source/drain contacts positioned on opposite sides of the gate structure, performing a common etching process sequence to define a gate contact opening that extends through the reduced-thickness portion of the gate cap layer and a plurality of separate source/drain contact openings in the layer of insulating material, and forming a conductive gate contact structure and conductive source/drain contact structures.

    Abstract translation: 本文公开的一种方法包括在材料层中形成开口以暴露晶体管的源极/漏极区域和位于有源区域上方的栅极覆盖层的第一部分，从而减小栅极帽部分的厚度 位于隔离区域上方的层，限定位于栅极结构的相对侧上的单独的初始源极/漏极触点，执行公共蚀刻工艺序列以限定延伸穿过栅极盖层的厚度减小的部分的栅极接触开口，以及 绝缘材料层中的多个独立的源极/漏极接触开口，以及形成导电栅极接触结构和导电源极/漏极接触结构。

    FINFET SEMICONDUCTOR DEVICES WITH STRESSED LAYERS
    19.
    发明申请
    FINFET SEMICONDUCTOR DEVICES WITH STRESSED LAYERS 审中-公开
    FINFET半导体器件与受压层

    公开(公告)号：US20160043223A1

    公开(公告)日：2016-02-11

    申请号：US14922549

    申请日：2015-10-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Ryan Ryoung-han Kim ,  William J. Taylor, Jr.

    IPC: H01L29/78 ,  H01L23/528 ,  H01L23/522 ,  H01L29/06

    CPC classification number: H01L29/7846 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A device includes at least one fin defined in a semiconductor substrate, a raised isolation structure surrounding and laterally spaced apart from the fin, and a gate structure extending across and positioned around a first portion of the fin. A buried fin contact structure is positioned inside of the raised isolation structure and extends across, is positioned around, and conductively contacts a second portion of the fin. An upper surface of the buried fin contact structure is positioned level with or below an upper surface of the raised isolation structure. A stress-inducing material layer is positioned on and in contact with the upper surface of the buried fin contact structure, an insulating material layer is positioned above the stress-inducing material layer and the raised isolation structure, and a contact structure extends through at least the insulating and stress-inducing material layers and conductively contacts the buried fin contact structure.

    Abstract translation: 一种器件包括限定在半导体衬底中的至少一个翅片，围绕翅片围绕并横向间隔开的凸起隔离结构，以及延伸跨过翅片的第一部分并围绕其定位的栅极结构。 埋入的翅片接触结构位于升高的隔离结构的内部，并且延伸穿过翅片的第二部分并且定位在其周围并且导电地接触翅片的第二部分。 埋入式翅片接触结构的上表面位于升高的隔离结构的上表面的下方或下方。 应力诱导材料层定位在埋地鳍接触结构的上表面上并与其接触，绝缘材料层位于应力诱导材料层和凸起隔离结构之上，接触结构至少延伸穿过 绝缘和应力诱导材料层并且导电地接触埋地鳍接触结构。

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