公开(公告)号：US20150214331A1

公开(公告)日：2015-07-30

申请号：US14168112

申请日：2014-01-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/2018 ,  H01L21/28238 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

Abstract translation: 制造半导体器件的方法包括在半导体衬底上形成至少一个半导体鳍片。 在布置在散热片上的蚀刻停止层上形成多个栅极形成层。 多个栅极形成层包括由电介质材料形成的虚拟栅极层。 图案化多个栅极形成层以在蚀刻停止层上形成多个虚拟栅极元件。 每个伪栅极元件由电介质材料形成。 蚀刻形成在虚拟栅极元件上的间隔层，以在虚拟栅极元件的每个侧壁上形成间隔物。 位于每个伪栅元件之间的蚀刻停止层的一部分被蚀刻以暴露半导体鳍片的一部分。 半导体材料从半导体鳍片的暴露部分外延生长以形成源极/漏极区域。

公开(公告)号：US10297510B1

公开(公告)日：2019-05-21

申请号：US15962536

申请日：2018-04-25

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Soon-Cheon Seo ,  Fee Li Lie ,  Linus Jang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092

Abstract: A method for fabricating a multiple gate width structure for an integrated circuit is described. A fin on a semiconductor substrate with a first hard mask layer is covered by a first and second sacrificial gate each of which includes a second hard mask layer. Spacer layers and a dielectric layer are formed over the first and second sacrificial gate structures. The resulting structure is planarized so that the first and second sacrificial gate structures and the dielectric layer have coplanar top surfaces. The first and second sacrificial gate structures are removed to respectively form first and second trench recesses in the dielectric layer. The trench recesses are filled with a conductor to form permanent gate structures. A first permanent gate structure is formed in the first trench recess has a first length and a second permanent gate structure is formed in the second trench recess has a second length greater than the first length.

公开(公告)号：US09842741B2

公开(公告)日：2017-12-12

申请号：US15342794

申请日：2016-11-03

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Soon-cheon Seo ,  Linus Jang

IPC: H01L27/088 ,  H01L21/306 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84

CPC classification number: H01L21/30604 ,  H01L21/0274 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/0886 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785

Abstract: After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions.

公开(公告)号：US20170076954A1

公开(公告)日：2017-03-16

申请号：US15342794

申请日：2016-11-03

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Soon-cheon Seo ,  Linus Jang

IPC: H01L21/306 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/30604 ,  H01L21/0274 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/0886 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785

Abstract: After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions.

Abstract translation: 在衬底上形成半导体材料部分和栅极结构之后，在半导体材料部分和栅极结构上沉积介电材料层。 在电介质材料层上进行各向异性蚀刻以形成栅极间隔物，而掩模层保护半导体材料部分和栅极结构的外围部分以避免半导体表面的不期望的物理暴露。 可以进行选择性外延以在半导体材料部分上形成凸起的有源区。 通过介电材料层可以防止选择性外延期间的半导体生长缺陷的形成。 或者，可以在覆盖半导体材料部分的栅极结构上形成介电栅极间隔物之后执行选择性半导体沉积工艺。 半导体生长缺陷可以通过蚀刻去除，而掩模层保护半导体材料部分上的凸起的有源区。

公开(公告)号：US20160365425A1

公开(公告)日：2016-12-15

申请号：US14739662

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd. ,  Globalfoundries Inc.

Inventor： Hsueh-Chung Chen ,  Su Chen Fan ,  Dong Kwon Kim ,  Sean Lian ,  Fee Li Lie ,  Linus Jang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L29/6653 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/3086 ,  H01L21/31116

Abstract: An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.

Abstract translation: 本发明的一个方面包括具有用于侧壁图像转印过程的亚光刻尺寸的独立间隔物。 独立间隔件包括：第一间隔层，其具有设置在半导体层上的第一部分; 以及第二间隔层，其具有设置在第一间隔层的第一部分上的第一表面，其中第一间隔层具有第一介电常数，第二间隔层具有第二介电常数，第一介电常数大于第二间隔层 介电常数，并且其中第一和第二间隔层中的每一个的尺寸共同确定独立间隔物的亚光刻横向尺寸。

公开(公告)号：US08871649B2

公开(公告)日：2014-10-28

申请号：US13834946

申请日：2013-03-15

Applicant: GLOBAL FOUNDRIES Inc. ,  Renesas Electronics Corporation ,  International Business Machines Corporation

Inventor： Linus Jang ,  Yoshinori Matsui ,  Chiahsun Tseng

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144

Abstract: One illustrative method disclosed herein involves forming a layer of insulating material, forming a patterned layer of photoresist above the layer of insulating material, wherein the patterned layer of photoresist has an opening defined therein, forming an internal spacer within the opening in the patterned layer of photoresist, wherein the spacer defines a reduced-size opening, performing an etching process through the reduced-size opening on the layer of insulating material to define a trench/hole type feature in the layer of insulating material, and forming a conductive structure in the trench/hole type feature in the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括形成绝缘材料层，在绝缘材料层之上形成图案化的光致抗蚀剂层，其中所述图案化的光致抗蚀剂层具有限定在其中的开口，在图案化层中的开口内形成内部间隔物 光致抗蚀剂，其中间隔物限定尺寸较小的开口，通过绝缘材料层上的尺寸减小的开口执行蚀刻工艺，以在绝缘材料层中限定沟槽/孔型特征，并在该层中形成导电结构 绝缘材料层中的沟槽/孔型特征。

公开(公告)号：US09209038B2

公开(公告)日：2015-12-08

申请号：US14267959

申请日：2014-05-02

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Ryan Ryoung-Han Kim

IPC: H01L21/00 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L21/823431

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a patternable structure having first and second regions and including upper and lower mandrel layers. The method etches upper mandrels from the upper mandrel layer in the first and second regions. The method includes forming first upper spacer structures having a first width adjacent upper mandrels in the first region and forming second upper spacer structures having a second width not equal to the first width adjacent upper mandrels in the second region. The method etches the lower mandrel layer using the first and second upper spacer structures as an etch mask to form lower mandrels. Further, the method includes forming spacers adjacent the lower mandrels and etching a material using the spacers as an etch mask to form variably spaced features.

Abstract translation: 提供了制造集成电路和形成用于制造集成电路的掩模的方法。 一种用于制造集成电路的示例性方法包括提供具有第一和第二区域并且包括上部和下部心轴层的可图案化结构。 该方法在第一和第二区域中从上心轴层蚀刻上心轴。 该方法包括形成在第一区域中具有与上心轴相邻的第一宽度的第一上间隔结构，并且形成第二上间隔结构，其具有不等于第二区中相邻上心轴的第一宽度的第二宽度。 该方法使用第一和第二上间隔结构蚀刻下心轴层作为蚀刻掩模以形成下心轴。 此外，该方法包括形成邻近下心轴的间隔物，并使用间隔物蚀刻材料作为蚀刻掩模以形成可变间隔的特征。

公开(公告)号：US08716094B1

公开(公告)日：2014-05-06

申请号：US13682769

申请日：2012-11-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Seo Park ,  Linus Jang ,  Jin Cho

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/311

CPC classification number: H01L29/66742 ,  H01L29/66795

Abstract: Approaches for forming a FinFET device using double patterning memorization techniques are provided. Specifically, a device will initially be formed by defining a set of fins, depositing a poly-silicon layer, and depositing a hardmask. Thereafter, a front end of the line (FEOL) lithography-etch, lithography-etch (LELE) process will be performed to form a set of trenches in the device. The set of trenches will be filled with an oxide layer that is subsequently polished. Thereafter, the device is selectively etched to yield a (e.g., poly-silicon) gate pattern.

Abstract translation: 提供了使用双重图案记忆技术形成FinFET器件的方法。 具体来说，首先将通过限定一组翅片，沉积多晶硅层和沉积硬掩模来形成器件。 此后，将执行线的前端（FEOL）光刻蚀刻，光刻蚀刻（LELE）处理以在器件中形成一组沟槽。 该组沟槽将填充随后抛光的氧化物层。 此后，选择性地蚀刻器件以产生（例如，多晶硅）栅极图案。

公开(公告)号：US09209037B2

公开(公告)日：2015-12-08

申请号：US14196931

申请日：2014-03-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Jin Cho ,  Ryan Ryoung-Han Kim

IPC: H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/845

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming fin structures in a selected area of a semiconductor substrate. The method includes covering the fin structures and the semiconductor substrate with a mask and forming a trench in the mask to define no more than two exposed fin structures in the selected area. Further, the method includes removing the exposed fin structures to provide the selected area with a desired number of fin structures.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括在半导体衬底的选定区域中形成鳍结构。 该方法包括用掩模覆盖翅片结构和半导体衬底，并在掩模中形成沟槽，以在所选择的区域中限定不超过两个暴露的翅片结构。 此外，该方法包括去除暴露的翅片结构以向选定区域提供所需数量的翅片结构。

公开(公告)号：US20140273443A1

公开(公告)日：2014-09-18

申请号：US13834946

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC. ,  RENESAS ELECTRONICS CORPORATION ,  INTERNATIONL BUSINESS MACHINES CORPORATION

Inventor： Linus Jang ,  Yoshinori Matsui ,  Chiahsun Tseng

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144

Abstract: One illustrative method disclosed herein involves forming a layer of insulating material, forming a patterned layer of photoresist above the layer of insulating material, wherein the patterned layer of photoresist has an opening defined therein, forming an internal spacer within the opening in the patterned layer of photoresist, wherein the spacer defines a reduced-size opening, performing an etching process through the reduced-size opening on the layer of insulating material to define a trench/hole type feature in the layer of insulating material, and forming a conductive structure in the trench/hole type feature in the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括形成绝缘材料层，在绝缘材料层之上形成图案化的光致抗蚀剂层，其中所述图案化的光致抗蚀剂层具有限定在其中的开口，在图案化层中的开口内形成内部间隔物 光致抗蚀剂，其中间隔物限定尺寸较小的开口，通过绝缘材料层上的尺寸减小的开口执行蚀刻工艺，以在绝缘材料层中限定沟槽/孔型特征，并在该层中形成导电结构 绝缘材料层中的沟槽/孔型特征。