公开(公告)号：US09960256B2

公开(公告)日：2018-05-01

申请号：US14282089

申请日：2014-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei

IPC: H01L21/44 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L29/66795 ,  H01L21/76804 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/66 ,  H01L29/785

Abstract: Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.

公开(公告)号：US09660040B2

公开(公告)日：2017-05-23

申请号：US14926657

申请日：2015-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L29/94 ,  H01L29/417 ,  H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

公开(公告)号：US20170047247A1

公开(公告)日：2017-02-16

申请号：US15336589

申请日：2016-10-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Mark A. Zaleski

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76834 ,  H01L21/31144 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76838 ,  H01L21/76897 ,  H01L23/52 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. Spacers are formed on each Mx+1 sacrificial line. The gap between the spacers is used to determine the location and thickness of cuts to the Mx metal lines. This ensures that the Mx metal line cuts do not encroach on vias that interconnect the Mx and Mx+1 levels. It also allows for reduced limits in terms of via enclosure rules, which enables increased circuit density.

Abstract translation: 本发明的实施例提供了一种在线结构的后端中自对准金属切割的方法。 牺牲Mx + 1线形成在金属Mx线之上。 每个Mx + 1牺牲线上形成间隔。 使用间隔件之间的间隙来确定切割到Mx金属线的位置和厚度。 这样可确保Mx金属线切割不会侵入连接Mx和Mx + 1电平的通孔。 它还允许通过外壳规则降低限制，从而增加电路密度。

公开(公告)号：US09502528B2

公开(公告)日：2016-11-22

申请号：US14469014

申请日：2014-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Mark A. Zaleski ,  Andy Chih-Hung Wei

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653

Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s).

Abstract translation: 提供了一种在半导体结构中提供改进的晶体管触点的改进的半导体结构和制造方法。 在半导体结构的一部分上形成第一块掩模。 该第一块掩模覆盖至少一个源/漏（s / d）接触位置的至少一部分。 在未被第一块掩模覆盖的s / d接触位置上形成s / d覆盖层。 该s / d封盖层由第一封盖物质构成。 然后，在半导体结构上形成第二块掩模。 该第二块掩模暴露至少一个门位置。 包括第二封盖物质的栅极覆盖层从暴露的栅极位置移除。 然后沉积金属接触层，其形成与s / d接触位置和栅极接触位置的接触。

公开(公告)号：US09390979B2

公开(公告)日：2016-07-12

申请号：US14482529

申请日：2014-09-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Huy M. Cao ,  Jing Wan

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L27/088 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823437 ,  H01L27/088

Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A set of masks is formed over a portion of the semiconductor structure. Each mask in this set of masks covers at least one source/drain (s/d) contact location. An oxide layer is removed from remainder portions of the semiconductor structure that are not covered by the set of masks. Then an opposite-mask fill layer is formed in the remainder portions from which the oxide layer was removed. The oxide layer is then removed from the remainder of the semiconductor structure, i.e., the portion previously covered by the set of masks and contacts are formed to the at least s/d contact location in the recesses formed by the removal of the remainder of the oxide layer.

Abstract translation: 提供了一种在半导体结构中提供改进的晶体管触点的改进的半导体结构和制造方法。 在半导体结构的一部分上形成一组掩模。 这组掩模中的每个掩模覆盖至少一个源/漏（s / d）接触位置。 从半导体结构的未被该组掩模覆盖的其余部分去除氧化物层。 然后在除去氧化物层的剩余部分中形成相对掩模填充层。 然后从半导体结构的其余部分去除氧化物层，即，先前被该组掩模和触点覆盖的部分形成在通过去除其余部分形成的凹部中的至少s / d接触位置 氧化层。

公开(公告)号：US09202751B2

公开(公告)日：2015-12-01

申请号：US14246476

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L21/338 ,  H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

Abstract translation: 本发明的实施例提供一种改进的半导体结构和制造方法，其提供在两维中自对准的晶体管接触。 使用两个不同的封盖层，每个覆盖层由不同的材料组成。 两个封盖层可以相互选择性地蚀刻。 一个覆盖层用于栅极覆盖，而另一个覆盖层用于源极/漏极覆盖。 选择性蚀刻工艺打开所需的栅极和源极/漏极，而块掩模用于覆盖不是连接方案一部分的元件。 沉积金属化线（层），与开放元件接触以提供它们之间的电连接。

公开(公告)号：US09196499B2

公开(公告)日：2015-11-24

申请号：US14225542

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Dae-han Choi ,  Dae Geun Yang ,  Xiang Hu ,  Mariappan Hariharaputhiran

IPC: H01L21/475 ,  H01L21/308 ,  H01L21/311 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/475 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.

Abstract translation: 本发明的实施例提供了从finFET去除翅片部分的方法。 在起始点，高K电介质层设置在基板上。 翅片硬掩模和光刻叠层沉积在高k电介质上。 翅片硬掩模被暴露，并且鳍状硬标记的第一部分被去除。 去除光刻叠层。 拆下散热片硬掩模的第二部分。 鳍形成。 间隙填充电介质被沉积并凹进。

公开(公告)号：US20150311199A1

公开(公告)日：2015-10-29

申请号：US14264240

申请日：2014-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei

IPC: H01L27/088 ,  H01L23/532 ,  H01L23/528 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L29/161 ,  H01L23/4824 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.

Abstract translation: 本发明的实施例提供具有低电阻栅极结构的多鳍场效应晶体管（finFET）。 金属化线与栅极平行地形成，并且多个触点形成在将金属化线连接到栅极的鳍上。 金属化线提供降低的栅极电阻，这允许更少的晶体管用于提供输入输出（IO）功能，从而提供节省空间以实现电路密度的增加。

公开(公告)号：US20150270175A1

公开(公告)日：2015-09-24

申请号：US14219059

申请日：2014-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Andy Chih-Hung Wei ,  Dae-han Choi ,  Mariappan Hariharaputhiran ,  Weihua Tong ,  Dae Geun Yang ,  Akshey Sehgal ,  Jing Wan

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/306 ,  H01L21/324 ,  H01L29/78 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/268 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/66795

Abstract: Provided herein are approaches for forming a fin field-effect-transistor (FinFET) device using a partially crystallized fin hard mask. Specifically, a hard mask is patterned over a substrate, and the FinFET device is annealed to form a set of crystallized hard mask elements adjacent a set of non-crystallized hard mask elements. A masking structure is provided over a first section of the patterned hard mask to prevent the set of non-crystallized hard mask elements from being crystallized during the anneal. During a subsequent fin cut process, the non-crystallized mask elements are removed, while crystallized mask elements remain. A set of fins is then formed in the FinFET device according to the location(s) of the crystallized mask elements.

Abstract translation: 本文提供了使用部分结晶的翅片硬掩模形成鳍状场效应晶体管（FinFET）器件的方法。 具体地说，将硬掩模图案化在衬底上，并且FinFET器件被退火以形成与一组非结晶硬掩模元件相邻的一组结晶的硬掩模元件。 在图案化的硬掩模的第一部分上提供掩模结构，以防止在退火期间该组非结晶硬掩模元件结晶。 在随后的翅片切割过程中，除去未结晶的掩模元件，同时保留结晶的掩模元件。 然后根据结晶化掩模元件的位置在FinFET器件中形成一组翅片。

公开(公告)号：US20200286998A1

公开(公告)日：2020-09-10

申请号：US16883492

申请日：2020-05-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei

IPC: H01L29/161 ,  H01L29/16 ,  H01L23/482 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.