公开(公告)号：US20200066585A1

公开(公告)日：2020-02-27

申请号：US16106246

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean Xuan Lin ,  Christian Witt ,  Mark V. Raymond ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/532

Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.

公开(公告)号：US20180366372A1

公开(公告)日：2018-12-20

申请号：US15626321

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet H. Suvarna ,  Steven Bentley ,  Mark V. Raymond ,  Peter M. Zeitzoff

IPC: H01L21/8234 ,  H01L21/285 ,  H01L27/088 ,  H01L29/45 ,  H01L29/78 ,  H01L29/08

Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.

公开(公告)号：US20180315821A1

公开(公告)日：2018-11-01

申请号：US15581053

申请日：2017-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45

Abstract: One illustrative method disclosed includes, among other things, forming a conductive source/drain metallization structure adjacent a gate, forming a gate contact opening that exposes at least a portion of a front face of the conductive source/drain metallization structure and a portion of an upper surface of a gate structure of the gate. In this example, the method further includes forming an internal insulating spacer within the gate contact opening that is positioned on and in contact with the exposed portion of the front face, wherein the spacer leaves at least a portion of the upper surface of the gate structure exposed, and forming a conductive gate contact structure (CB) in the conductive gate contact opening.

公开(公告)号：US09679807B1

公开(公告)日：2017-06-13

申请号：US14948214

申请日：2015-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vimal Kamineni ,  Mark V. Raymond ,  Praneet Adusumilli ,  Chengyu Niu

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/67207 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/45 ,  H01L29/78

Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.

公开(公告)号：US20140167264A1

公开(公告)日：2014-06-19

申请号：US13714049

申请日：2012-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Paul R. Besser ,  Mark V. Raymond ,  Valli Arunachalam ,  Hoon Kim

IPC: H01L21/283 ,  H01L29/49

CPC classification number: H01L29/4916 ,  H01L21/28518 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括提供半导体衬底并在半导体衬底上形成翅片。 每个翅片形成有侧壁。 该方法还包括在每个翅片的侧壁上共形沉积金属膜堆叠。 在该方法中，金属膜堆叠被退火以在每个翅片的侧壁上形成金属硅化物膜。

公开(公告)号：US10580696B1

公开(公告)日：2020-03-03

申请号：US16106246

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean Xuan Lin ,  Christian Witt ,  Mark V. Raymond ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L23/12 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532 ,  H01L21/288

Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.

公开(公告)号：US20190378900A1

公开(公告)日：2019-12-12

申请号：US16548335

申请日：2019-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/45

Abstract: One device disclosed herein includes a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap, and conductive source/drain metallization structures adjacent the gate, each of the conductive source/drain metallization structures having a front face and a recess defined in each of the conductive source/drain metallization structures. In this example, the device further includes a spacer structure comprising recess filling portions that substantially fill the recesses and a portion that extends across a portion of the upper surface of the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, an insulating material within the spacer structure and on the exposed portion of the gate cap, a gate contact opening that exposes a portion of an upper surface of the gate structure, and a conductive gate contact structure in the conductive gate contact opening.

公开(公告)号：US20190081145A1

公开(公告)日：2019-03-14

申请号：US15701678

申请日：2017-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Nigel G. Cave ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: A structure and method for forming sets of contact structures to source/drain regions of complimentary N-type field effect transistors (NFETs) and P-type field effect transistors (PFETs). The structure including a NFET structure including a first fin positioned on a substrate and a PFET structure including a second fin positioned on the substrate, wherein a source/drain region (S/D) of the first fin and a S/D of the second fin include non-uniform openings at an uppermost surface. A method of forming non-uniformly openings in the S/Ds of the complimentary NFETs and PFETs including forming mask on the PFET to protect the structure during formation of openings in the NFET S/D. A method of forming non-uniform openings in the S/D of the complimentary NFETs and PFETs including reducing the epitaxially growth of the NFET S/D to form an opening therein.

公开(公告)号：US20190027580A1

公开(公告)日：2019-01-24

申请号：US15655547

申请日：2017-07-20

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Chen Fan ,  Andrew M. Greene ,  Sean Lian ,  Balasubramanian Pranatharthiharan ,  Mark V. Raymond ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/033 ,  H01L21/768 ,  H01L21/285

Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.

公开(公告)号：US20180286956A1

公开(公告)日：2018-10-04

申请号：US15477565

申请日：2017-04-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Andre P. Labonte ,  Lars W. Liebmann ,  Nigel G. Cave ,  Mark V. Raymond ,  Guillaume Bouche ,  David E. Brown

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

CPC classification number: H01L29/41775 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/66545

Abstract: One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a stepped final gate structure with a second recess defined therein, wherein, when viewed from above, the second recess is axially and laterally offset from the first recess. In this example, the device also includes a layer of insulating material positioned above the stepped conductive source/drain structure and the stepped final gate structure, a conductive gate (CB) contact that is conductively coupled to the stepped final gate structure and a conductive source/drain (CA) contact that is conductively coupled to the stepped conductive source/drain structure.