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    LOCALIZED MASKING FOR SEMICONDUCTOR STRUCTURE DEVELOPMENT
    12.
    发明申请
    LOCALIZED MASKING FOR SEMICONDUCTOR STRUCTURE DEVELOPMENT 有权
    用于半导体结构开发的本地化掩模

    公开(公告)号：US20090102018A1

    公开(公告)日：2009-04-23

    申请号：US12276152

    申请日：2008-11-21

    Applicant: Donald L. Yates ,  Garry A. Mercaldi

    Inventor： Donald L. Yates ,  Garry A. Mercaldi

    IPC: H01L29/92

    CPC classification number: H01L28/92 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/32139 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

    Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

    Abstract translation: 用于集成电路的容器结构及其制造方法，而不使用机械平面化（例如化学机械平面化（CMP）），从而消除了CMP引起的缺陷和变化。 该方法利用在非机械去除暴露的表面层期间的孔的局部掩蔽来保护孔的内部。 通过将抗蚀剂层与电磁或热能的差分曝光来实现局部掩蔽。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

    Enhanced surface area capacitor fabrication methods
    13.
    发明授权
    Enhanced surface area capacitor fabrication methods 失效
    增强表面积电容器制造方法

    公开(公告)号：US07112503B1

    公开(公告)日：2006-09-26

    申请号：US09653156

    申请日：2000-08-31

    Applicant: Vishnu K. Agarwal ,  Garry A. Mercaldi

    Inventor： Vishnu K. Agarwal ,  Garry A. Mercaldi

    IPC: H01L21/20

    CPC classification number: H01L28/55 ,  H01L21/31604 ,  H01L21/31683 ,  H01L28/84 ,  H01L28/90 ,  Y10S438/964

    Abstract: A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. The barrier layer may be sufficiently thick and dense to reduce oxidation of the first electrode by oxygen diffusion from over the barrier layer. An alternative method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer. The method may further include forming rugged polysilicon over the substrate, the first electrode being over the rugged polysilicon. Accordingly, the outer surface area of the first electrode can be at least 30% greater than the outer surface area of the substrate without the first electrode including polysilicon.

    Abstract translation: 电容器制造方法可以包括在第一电极上的氧扩散的原子层沉积导电阻挡层。 一种方法可以包括在第一电极上化学吸附至少一层单层的第一前体层，并化学吸附第一前体层上至少一层单层的第二前体层，第一和第二前体层的化学吸附产物 由导电阻挡材料层组成。 阻挡层可以是足够厚且致密的，以通过从阻挡层上方的氧扩散来减少第一电极的氧化。 替代方法可以包括在衬底上形成第一电容器电极，第一电极具有每单位面积的内表面积和每单位面积的外表面积，其大于衬底每单位面积的外表面积。 可以在电介质层上形成电容器电介质层和第二电容器电极。 该方法还可以包括在衬底上形成坚固的多晶硅，第一电极在坚固的多晶硅之上。 因此，第一电极的外表面积可以比不含第一电极包括多晶硅的衬底的外表面积大至少30％。

    Low selectivity deposition methods
    15.
    发明授权
    Low selectivity deposition methods 失效

    公开(公告)号：US06987073B2

    公开(公告)日：2006-01-17

    申请号：US10299140

    申请日：2002-11-18

    Applicant: Garry A. Mercaldi

    Inventor： Garry A. Mercaldi

    IPC: H01L21/31

    CPC classification number: H01L21/02271 ,  C23C16/0272 ,  C23C16/45525 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/0228 ,  H01L21/3185 ,  H01L28/84 ,  H01L28/91

    Abstract: A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the first substance. The chemisorption product of the first and second substance may include silicon and nitrogen. The nucleation layer may comprise silicon nitride. Further, a deposition method may include forming a first part of a nucleation layer on a first surface of a substrate and forming a second part of a nucleation layer on a second surface of the substrate. A deposition layer may be formed on the first and second parts of the nucleation layer substantially non-selectively on the first part of the nucleation layer compared to the second part. The first surface may be a surface of a borophosphosilicate glass layer. The second surface may be a surface of a rugged polysilicon layer. The first and second part of the nucleation layer may be formed simultaneously.

    Semiconductor processing methods and semiconductor defect detection methods
    16.
    发明授权
    Semiconductor processing methods and semiconductor defect detection methods 失效
    半导体处理方法和半导体缺陷检测方法

    公开(公告)号：US06417015B2

    公开(公告)日：2002-07-09

    申请号：US09870157

    申请日：2001-05-29

    Applicant: Michael Nuttall ,  Garry A. Mercaldi

    Inventor： Michael Nuttall ,  Garry A. Mercaldi

    IPC: H01L2166

    CPC classification number: H01L22/24 ,  Y10S438/928 ,  Y10S438/974

    Abstract: Semiconductor processing methods and defect detection methods are described. In one embodiment, a semiconductor wafer in process is provided and a material is formed or deposited over the wafer. The material is discernably deposited over defective wafer surface areas and not appreciably deposited over non-defective wafer surface areas. Subsequently, the wafer surface areas are inspected to identify defective areas. In another embodiment, a substrate is provided having an exposed region containing surface defects. A defect-highlighting material is substantially selectively deposited over surface defects and not appreciably over other exposed regions. The substrate is subsequently inspected for the deposited defect-highlighting material. In yet another embodiment, a dielectric layer is formed over a substrate outer surface and the substrate is processed in a manner which can give rise to a plurality of randomly-distributed dielectric layer features. A silicon-containing material is substantially selectively deposited and received over the randomly distributed dielectric layer features and not over other substrate areas. The substrate is subsequently inspected for the selectively-deposited silicon containing material.

    Abstract translation: 描述半导体处理方法和缺陷检测方法。 在一个实施例中，提供了工艺中的半导体晶片，并且在晶片上形成或沉积材料。 该材料可辨别地沉积在缺陷晶片表面区域上，并且不会明显地沉积在无缺陷晶片表面区域上。 随后，检查晶片表面区域以识别缺陷区域。 在另一个实施例中，提供具有包含表面缺陷的暴露区域的衬底。 缺陷突出材料基本上选择性地沉积在表面缺陷上，而不是明显地超过其它暴露区域。 随后检查衬底以便沉积的缺陷突出材料。 在另一个实施例中，在衬底外表面上形成电介质层，并且以可以产生多个随机分布的电介质层特征的方式处理衬底。 基本上选择性地沉积含硅材料并将其接收在随机分布的介电层特征上而不是在其它衬底区域上。 随后检查衬底以选择沉积含硅材料。

    Semiconductor processing methods and semiconductor defect detection methods
    17.
    发明授权
    Semiconductor processing methods and semiconductor defect detection methods 失效
    半导体处理方法和半导体缺陷检测方法

    公开(公告)号：US06387716B1

    公开(公告)日：2002-05-14

    申请号：US09522054

    申请日：2000-03-09

    Applicant: Michael Nuttall ,  Garry A. Mercaldi

    Inventor： Michael Nuttall ,  Garry A. Mercaldi

    IPC: H01L2166

    CPC classification number: H01L22/24 ,  Y10S438/928 ,  Y10S438/974

    Abstract: Semiconductor processing methods and defect detection methods are described. In one embodiment, a semiconductor wafer in process is provided and a material is formed or deposited over the wafer. The material is discernably deposited over defective wafer surface areas and not appreciably deposited over non-defective wafer surface areas. Subsequently, the wafer surface areas are inspected to identify defective areas. In another embodiment, a substrate is provided having an exposed region containing surface defects. A defect-highlighting material is substantially selectively deposited over surface defects and not appreciably over other exposed regions. The substrate is subsequently inspected for the deposited defect-highlighting material. In yet another embodiment, a dielectric layer is formed over a substrate outer surface and the substrate is processed in a manner which can give rise to a plurality of randomly-distributed dielectric layer features. A silicon-containing material is substantially selectively deposited and received over the randomly-distributed dielectric layer features and not over other substrate areas. The substrate is subsequently inspected for the selectively-deposited silicon-containing material.

    Abstract translation: 描述半导体处理方法和缺陷检测方法。 在一个实施例中，提供了工艺中的半导体晶片，并且在晶片上形成或沉积材料。 该材料可辨别地沉积在缺陷晶片表面区域上，并且不会明显地沉积在无缺陷晶片表面区域上。 随后，检查晶片表面区域以识别缺陷区域。 在另一个实施例中，提供具有包含表面缺陷的暴露区域的衬底。 缺陷突出材料基本上选择性地沉积在表面缺陷上，而不是明显地超过其它暴露区域。 随后检查衬底以便沉积的缺陷突出材料。 在另一个实施例中，在衬底外表面上形成电介质层，并且以可以产生多个随机分布的电介质层特征的方式处理衬底。 基本上选择性地沉积含硅材料并将其接收在无规分布的介电层特征上而不是在其它基底区域上。 随后检查衬底以进行选择性沉积的含硅材料。

    Method for optimization of thin film deposition
    19.
    发明授权
    Method for optimization of thin film deposition 失效
    薄膜沉积优化方法

    公开(公告)号：US5976990A

    公开(公告)日：1999-11-02

    申请号：US004931

    申请日：1998-01-09

    Applicant: Garry A. Mercaldi ,  Michael L. Nuttall ,  Randhir P. S. Thankur

    Inventor： Garry A. Mercaldi ,  Michael L. Nuttall ,  Randhir P. S. Thankur

    IPC: C23C16/34 ,  C23C16/44 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/31 ,  H01L21/469

    CPC classification number: H01L21/0217 ,  C23C16/345 ,  C23C16/44 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/31604 ,  H01L21/31691 ,  H01L28/90

    Abstract: An exemplary implementation of the present invention discloses a semiconductor fabrication method for forming a film in a reactor. Process conditions (temperature and pressure) are initially stabilized prior to a film deposition cycle. Once process conditions are stable, chemical elements of are nucleated onto a substrate surface to form a nucleation surface of the film. The bulk portion of the film is then deposited onto the nucleation surface. Finally, after the bulk of the film is deposited the surface of the film is conditioned. To tailor a film the process conditions are varied during the film deposition cycle wherein at least one of the pressures and temperatures is varied by at least 10%. In a specific implementation, a capacitor dielectric of silicon nitride is tailored by varying the pressure for the bulk film deposition and by varying both the temperature and pressure for the film surface formation phase.

    Abstract translation: 本发明的示例性实施方式公开了一种用于在反应器中形成膜的半导体制造方法。 在膜沉积循环之前，工艺条件（温度和压力）最初是稳定的。 一旦工艺条件稳定，将化学元素成核到基底表面上以形成膜的成核表面。 然后将膜的主体部分沉积到成核表面上。 最后，在沉积膜的大部分之后，调节膜的表面。 为了定制薄膜，工艺条件在成膜周期期间是变化的，其中至少一个压力和温度变化至少10％。 在具体实施方式中，氮化硅的电容器电介质通过改变体膜沉积的压力并通过改变膜表面形成阶段的温度和压力来调整。

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