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126 条记录 (耗时 0.043 秒)

    2,5-diketo-D-gluconic acid (2,5-DKG) permeases
    13.
    发明授权
    2,5-diketo-D-gluconic acid (2,5-DKG) permeases 有权
    2,5-二酮-D-葡萄糖酸（2,5-DKG）渗透酶

    公开(公告)号：US07229811B2

    公开(公告)日：2007-06-12

    申请号：US10343369

    申请日：2001-08-03

    申请人： Manoj Kumar ,  Fernando Valle ,  Veronique A. Dartois ,  James A. Hoch

    发明人： Manoj Kumar ,  Fernando Valle ,  Veronique A. Dartois ,  James A. Hoch

    IPC分类号： C07H21/04 ,  C12N15/00 ,  C12N1/20 ,  C12P7/40 ,  C12P21/06 ,  C12Q1/26 ,  C07K14/00 ,  C12P19/34 ,  C12N9/04

    CPC分类号： C07K14/26 ,  C07K14/24

    摘要： The invention provides isolated nucleic acid molecules encoding polypeptides having 2,5-DKG permease activity, and oligonucleotides therefrom. The isolated nucleic acid molecules can be expressed in appropriate bacterial cells to enhance the production of 2-KLG, which can subsequently be converted to ascorbic acid. Further provided are isolated polypeptides having 2,5-DKG permease acitivity, immunogenic peptides therefrom, and antibodies specific therefor. The invention also provides methods of identifying novel 2,5-DKG permeases.

    摘要翻译： 本发明提供了编码具有2,5-DKG通透酶活性的多肽的分离的核酸分子及其寡核苷酸。 分离的核酸分子可以在适当的细菌细胞中表达以增强2-KLG的产生，随后将其转化为抗坏血酸。 还提供了具有2,5-DKG通透酶活性的分离的多肽，其免疫原性肽及其特异的抗体。 本发明还提供鉴定新型2,5-DKG通透酶的方法。

    Differential input receiver with hysteresis
    16.
    发明授权
    Differential input receiver with hysteresis 有权
    具有迟滞的差分输入接收器

    公开(公告)号：US06879198B2

    公开(公告)日：2005-04-12

    申请号：US10739879

    申请日：2003-12-18

    申请人： Manoj Kumar ,  Rajesh Narwal

    发明人： Manoj Kumar ,  Rajesh Narwal

    IPC分类号： H03K3/3565 ,  H03K3/037

    CPC分类号： H03K3/3565

    摘要： A differential input receiver with hysteresis on both sides of the reference voltage may include a two-input, one-output differential amplifier including two input transistors having a common terminal connected together. The control terminal of each transistor may be connected to one of the inputs of the differential amplifier. The output of the differential amplifier may be connected to a set of cascaded digital inverters/buffers, and an output of each digital buffer may be connected to the control terminal of a feedback transistor. The feedback transistor may be connected in parallel across each of the input transistors so that when one input voltage increases above or decreases below the input voltage at the second input by a predetermined threshold value, the feedback transistors operate to provide positive feedback to facilitate a rapid switching action at the output.

    摘要翻译： 具有参考电压两侧的迟滞的差分输入接收器可以包括双输入单输出差分放大器，其包括连接在一起的共同端子的两个输入晶体管。 每个晶体管的控制端可以连接到差分放大器的一个输入端。 差分放大器的输出可以连接到一组级联的数字反相器/缓冲器，并且每个数字缓冲器的输出可以连接到反馈晶体管的控制端子。 反馈晶体管可以并联连接在每个输入晶体管上，使得当一个输入电压在第二输入处增加到或低于第二输入处的输入电压以下预定阈值时，反馈晶体管操作以提供正反馈以促进快速 在输出端切换动作。

    Production of ascorbic acid
    17.
    发明授权
    Production of ascorbic acid 失效

    公开(公告)号：US06824996B2

    公开(公告)日：2004-11-30

    申请号：US10026139

    申请日：2001-12-18

    申请人： Manoj Kumar

    发明人： Manoj Kumar

    IPC分类号： G01N3353

    CPC分类号： C12P7/04 ,  C12N1/16

    摘要： The present invention provides for the production of ASA from yeast capable of producing ASA from KLG. The present invention provides methods for the production of ASA as well as recombinant yeast capable of producing ASA from a carbon source.

    Data processing system for controlling operation of a sense amplifier in a cache
    18.
    发明授权
    Data processing system for controlling operation of a sense amplifier in a cache 失效
    用于控制缓存中的读出放大器的操作的数据处理系统

    公开(公告)号：US6016534A

    公开(公告)日：2000-01-18

    申请号：US887825

    申请日：1997-07-30

    申请人： Manoj Kumar ,  Huy Van Pham

    发明人： Manoj Kumar ,  Huy Van Pham

    IPC分类号： G11C11/419 ,  G11C15/04 ,  G06F13/00 ,  G11C11/413

    CPC分类号： G11C11/419 ,  G11C15/04

    摘要： A cache memory device having circuitry for controlling operation of a sense amplifier for accessing an array in the data processing system including a cache memory device includes circuitry for enabling the sense amplifier when there is a hit in the array as a result of a read request and disables the sense amplifier when there is a miss in the array as a result of the read request. The cache memory device may receives an address associated with the read request, and compares the address to addresses associated with entries in the array, wherein a hit results when the received address matches at least one of the addresses associated with the entries in the array, and wherein a miss results when the received address does not match at least one of the addresses associated with the entries in the array. The address associated with the read request and the addresses associated with entries in the array are effective addresses. The cache memory device may enable the sense amp only when the array is being accessed by the read request, and only after an entire address associated with the read request has been received.

    摘要翻译： 一种具有用于控制读取放大器的操作的电路的高速缓冲存储器件，该读出放大器用于访问数据处理系统中包括高速缓存存储器件的阵列，该电路包括用于当由于读取请求而在阵列中存在命中时能够使读出放大器工作的电路， 由于读取请求，当数组中存在缺失时，禁用读出放大器。 高速缓冲存储器设备可以接收与读取请求相关联的地址，并且将地址与与阵列中的条目相关联的地址进行比较，其中当接收到的地址匹配与阵列中的条目相关联的至少一个地址时， 并且其中当接收到的地址与与阵列中的条目相关联的至少一个地址不匹配时，导致未命中。 与读取请求相关联的地址和与数组中的条目相关联的地址是有效地址。 高速缓冲存储器装置可以仅在读取请求访问阵列时才能使能感测放大器，并且只有在已经接收到与读取请求相关联的整个地址之后才能使能该读出放大器。

    Write driver and bit line precharge apparatus and method
    19.
    发明授权
    Write driver and bit line precharge apparatus and method 失效
    写入驱动器和位线预充电装置和方法

    公开(公告)号：US5959916A

    公开(公告)日：1999-09-28

    申请号：US19895

    申请日：1998-02-06

    申请人： Manoj Kumar

    发明人： Manoj Kumar

    IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/12 ,  G11C11/409 ,  G11C11/417 ,  G11C11/419 ,  G11C13/00 ,  G11C7/00

    CPC分类号： G11C7/1078 ,  G11C11/419 ,  G11C7/12

    摘要： A write driver apparatus (10) is adapted for producing a first data output signal and a second data output signal used in driving data onto a bit line pair (16, 18) associated with an electronic computer memory. The first and second data output signals represent desired data and are produced in response to a data signal, refill signal, and a data propagation clock signal. The data propagation signal is derived from system clock signals. A precharge circuit (12) associated with the write driver (10) operates in response to a precharge clock signal to precharge the bit lines (16, 18) prior to each read or write operation. The precharge clock signal is related to the data propagation signal to ensure that the bit lines (16, 18) are fully precharged prior to a read operation. A keeper circuit (14) associated with the bit lines (16, 18) also helps maintain a desired charge state on the bit lines during a read operation from memory cells (20) connected to the bit lines.

    摘要翻译： 写驱动器装置（10）适用于产生用于将数据驱动到与电子计算机存储器相关联的位线对（16,18）上的第一数据输出信号和第二数据输出信号。 第一和第二数据输出信号表示期望的数据，并且响应于数据信号，再填充信号和数据传播时钟信号产生。 数据传播信号来源于系统时钟信号。 与写入驱动器（10）相关联的预充电电路（12）响应于预充电时钟信号而工作，以在每次读或写操作之前对位线（16,18）进行预充电。 预充电时钟信号与数据传播信号相关，以确保位线（16,18）在读取操作之前被完全预充电。 与位线（16,18）相关联的保持器电路（14）还有助于在连接到位线的存储器单元（20）的读取操作期间在位线上保持期望的电荷状态。

    Cache memory having a selectable cache-line replacement scheme using cache-line registers in a ring configuration with a token indicator
    20.
    发明授权
    Cache memory having a selectable cache-line replacement scheme using cache-line registers in a ring configuration with a token indicator 失效
    具有可选择的高速缓存线替换方案的高速缓存存储器使用具有令牌指示符的环配置中的高速缓存行寄存器

    公开(公告)号：US5937429A

    公开(公告)日：1999-08-10

    申请号：US844550

    申请日：1997-04-21

    申请人： Manoj Kumar ,  Peichun Peter Liu ,  Huy Pham ,  Rajinder Paul Singh

    发明人： Manoj Kumar ,  Peichun Peter Liu ,  Huy Pham ,  Rajinder Paul Singh

    IPC分类号： G06F12/12

    CPC分类号： G06F12/127

    摘要： A cache memory having a selectable cache-line replacement scheme is described. In accordance with a preferred embodiment of the present invention, the cache memory has a number of cache lines, a number of token registers, a token, and a selection circuit. The token registers are connected to each other in a ring configuration. There is an equal number of token registers and cache lines, and each of the token registers is associated with one of the cache lines. The token is utilized to indicate one of the cache lines as a candidate for replacement by the associated token register in which the token settles. The selection circuit is associated with all of the token registers. This selection circuit provides at least two methods of controlling the movement of the token within the ring of the token registers, to be selectable during runtime. Each method of token movement represents a cache-line replacement scheme.

    摘要翻译： 描述了具有可选择的高速缓存线更换方案的高速缓冲存储器。 根据本发明的优选实施例，高速缓冲存储器具有多个高速缓存线，多个令牌寄存器，令牌和选择电路。 令牌寄存器以环形配置相互连接。 存在相等数量的令牌寄存器和高速缓存行，并且每个令牌寄存器与其中一个高速缓存行相关联。 令牌被用于将一个缓存行指示为由令牌结算的相关联的令牌寄存器替换的候选。 选择电路与所有令牌寄存器相关联。 该选择电路提供至少两种方法来控制令牌在令牌寄存器的环内的移动，以便在运行时期间可选择。 令牌移动的每种方法代表高速缓存行替换方案。