Abstract:
A data storage method, a storage apparatus and a computing device are disclosed. The method includes receiving a presetting command sent by a CPU, where the presetting command instructs to write 1 to a location, which corresponds to a cache line, in memory; writing, according to the presetting command, 1 to the location, which corresponds to the cache line, in the memory; receiving a write command sent by the CPU of writing data in the cache line to the memory; and writing, according to the write command, data 0 in the cache line to a location, which corresponds to the data 0, in the memory.
Abstract:
A hybrid storage device includes a controller, a volatile storage unit, and a non-volatile storage unit. When the hybrid storage device is in a first working mode, the volatile storage unit is in an enabled state, and the non-volatile storage unit is in a disabled state; when the hybrid storage device is in a second working mode, the non-volatile storage unit is in an enabled state, and the volatile storage unit is in a disabled state. When the hybrid storage device runs in the first working mode, and when detecting that a running parameter of the computer meets a first switching condition, the controller enables the non-volatile storage unit, copies data in the volatile storage unit to the non-volatile storage unit, and switches the hybrid storage device to the second working mode.
Abstract:
A circuit and an array circuit for implementing a shift operation are provided. The circuit for implementing a shift operation includes a resistive random-access memory and four switches. The circuit has a simple structure and can improve computational efficiency.
Abstract:
A first memory access request is obtained, where the first memory access request is used to request to access a first sub-row in a memory. A to-be-scheduled queue of the memory is searched for a second memory access request, where the to-be-scheduled queue of the memory includes multiple memory access requests, the second memory access request is used to request to access a second sub-row in the memory. The first sub-row and the second sub-row are located in a same row in the memory. The first memory access request and the second memory access request are combined to generate a first activation instruction, where the first activation instruction is used to instruct to activate the first sub-row and the second sub-row in the memory. The first activation instruction is sent to the memory.
Abstract:
A circuit and an array circuit for implementing a shift operation are provided. The circuit for implementing a shift operation includes a resistive random-access memory and four switches. The circuit has a simple structure and can improve computational efficiency.
Abstract:
A magnetic storage track and a magnetic memory are provided. The magnetic storage track includes multiple stacked storage track units. A transition layer is disposed between two neighboring storage track units. The transition layer is constituted by a semiconductor material deposited on an insulating material, and includes a gating circuit and a read/write apparatus. Because the magnetic storage track includes multiple stacked storage track units, a track length of the magnetic storage track is constituted by track lengths of the multiple storage track units. Therefore, when a storage capability of the magnetic storage track needs to be improved, the track length of the magnetic storage track may be increased by adding the storage track unit.
Abstract:
A storage unit includes a U-shaped magnetic track, a first drive circuit, a second drive circuit, a first drive port, and a second drive port. The U-shaped magnetic track includes a first port, a second port, a first storage area, and a second storage area. By controlling input voltages of the first port, the second port, the first drive port, and the second drive port and driving the first drive circuit, a current pulse is generated in the first storage area, and a magnetic domain wall in the first storage area is driven to move. By controlling the input voltages of the first port, the second port, the first drive port, and the second drive port and driving the second drive circuit, a current pulse is generated in the second storage area, and a magnetic domain in the second storage area is driven to move.
Abstract:
A circuit, where a first end of a resistive random access memory (RRAM) included in the circuit includes a first end of the circuit, and a second end of the RRAM is coupled to a first end of a first switch and a first end of a second switch, a second end of the first switch includes a second end of the circuit, and a first control end of the first switch and a second control end of the second switch are configured to make the first switch closed and the second switch open at the same time. Therefore, a working status of the RRAM is flexibly controlled.
Abstract:
A file management method, a distributed storage system, and a management node are disclosed. In the distributed storage system, after receiving a file creation request sent by a host for requesting to create a file in a distributed storage system, a management node allocates, to the file, first virtual space from global virtual address space of the distributed storage system, where local virtual address space of each storage node in the distributed storage system is corresponding to a part of the global virtual address space. Then, the management node records metadata of the file, where the metadata of the file includes information about the first virtual space, and the information about the first virtual space is used to point to local virtual address space of a storage node that is used to store the file. Further, the management node sends, the information about the first virtual space to the host.
Abstract:
A circuit, where a first end of a resistive random access memory (RRAM) included in the circuit includes a first end of the circuit, and a second end of the RRAM is coupled to a first end of a first switch and a first end of a second switch, a second end of the first switch includes a second end of the circuit, and a first control end of the first switch and a second control end of the second switch are configured to make the first switch closed and the second switch open at the same time. Therefore, a working status of the RRAM is flexibly controlled.