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31 条记录 (耗时 0.026 秒)

    On-chip RF shields with backside redistribution lines
    11.
    发明授权
    On-chip RF shields with backside redistribution lines 有权
    具有背面再分配线的片上RF屏蔽

    公开(公告)号：US07936052B2

    公开(公告)日：2011-05-03

    申请号：US12242487

    申请日：2008-09-30

    申请人： Hans-Joachim Barth ,  Jens Pohl ,  Gottfried Beer ,  Heinrich Koerner

    发明人： Hans-Joachim Barth ,  Jens Pohl ,  Gottfried Beer ,  Heinrich Koerner

    IPC分类号： H01L29/72

    CPC分类号： H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/552 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05569 ,  H01L2924/0002 ,  H01L2224/05552

    摘要： Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

    摘要翻译： 公开了一种片上系统的结构以及片上系统的形成方法。 在一个实施例中，一种制造片上系统的方法包括从衬底的背面形成穿透衬底开口，穿过衬底开口设置在第一和第二区域之间，第一区域包括用于RF电路的装置，第二区域包括第二 区域包括用于其他电路的装置。 该方法还包括在光致抗蚀剂层上形成用于再分配线的图案，设置在背面下方的光致抗蚀剂层，以及用导电材料填充贯通基板开口和再分配线图案。

    Integrated circuit arrangement with layer stack, and process
    13.
    发明申请
    Integrated circuit arrangement with layer stack, and process 有权
    集成电路布置与层叠，和过程

    公开(公告)号：US20060267205A1

    公开(公告)日：2006-11-30

    申请号：US11438080

    申请日：2006-05-19

    申请人： Heinrich Koerner

    发明人： Heinrich Koerner

    IPC分类号： H01L23/48 ,  H01L23/52

    CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit arrangement includes an electrically conductive conduction structure made from copper or a copper alloy. At a side wall of the conduction structure, there is a layer stack which includes at least three layers. Despite very thin layers in the layer stack, it is possible to achieve a high barrier action against copper diffusion combined with a high electrical conductivity, as is required for electrolytic deposition of copper using external current.

    摘要翻译： 集成电路装置包括由铜或铜合金制成的导电导电结构。 在导电结构的侧壁处，存在包括至少三层的层叠层。 尽管层叠中的层非常薄，但是可以实现与铜电极扩散相结合的高导电性的高屏障作用，如使用外部电流的铜电解沉积所需要的。