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    Methods and systems for high write performance in multi-bit flash memory devices
    16.
    发明授权
    Methods and systems for high write performance in multi-bit flash memory devices 有权

    公开(公告)号：US07206224B1

    公开(公告)日：2007-04-17

    申请号：US11037477

    申请日：2005-01-18

    申请人： Mark Randolph ,  Darlene Hamilton ,  Roni Kornitz

    发明人： Mark Randolph ,  Darlene Hamilton ,  Roni Kornitz

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0475 ,  G11C16/10 ,  G11C2211/5641

    摘要： Methods and circuits for performing high speed write (programming) operations in a dual-bit flash memory array. The method includes, for example, erasing a first and second bit of each cell in the array to a first state, programming the first bit of each cell in the array to a second state, and subsequently programming the second bit of one or more cells in the array to one of the first and second state according to the user's data, resulting in fast write (programming) of those second bits. In addition, the circuit includes, for example, a core cell array having dual-bit flash memory cells configured into a plurality of array portions. The circuit further includes a control circuit configured to selectively block erase one of the array portions, wherein in a first phase of the block erase both first and second bit locations of each dual-bit flash memory cell in the one array portion have sufficient charge removed therefrom to achieve a first state. The control circuit is further configured to, in a second phase of the block erase, supply charge to the first bit location of each dual-bit flash memory cell of the one array portion to enable subsequently fast-write of user's data to the second bit location.

    Flash memory cell and methods for programming and erasing
    17.
    发明申请
    Flash memory cell and methods for programming and erasing 有权

    公开(公告)号：US20060291282A1

    公开(公告)日：2006-12-28

    申请号：US11511763

    申请日：2006-08-29

    申请人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

    发明人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

    摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

    Read-only memory array with dielectric breakdown programmability
    18.
    发明申请
    Read-only memory array with dielectric breakdown programmability 审中-公开
    具有介电击穿可编程性的只读存储阵列

    公开(公告)号：US20060268593A1

    公开(公告)日：2006-11-30

    申请号：US11136981

    申请日：2005-05-25

    申请人： Meng Ding ,  Zhizheng Liu ,  Yi He ,  Mark Randolph

    发明人： Meng Ding ,  Zhizheng Liu ,  Yi He ,  Mark Randolph

    IPC分类号： G11C17/00

    CPC分类号： G11C17/16 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/118

    摘要： According to one exemplary embodiment, a programmable ROM array includes at least one bitline situated in a substrate. The programmable ROM array further includes at least one wordline situated over the at least one bitline. The programmable ROM array further includes a memory cell situated at an intersection of the at least one bitline and the at least one wordline, where the memory cell includes a dielectric region situated between the at least one bitline and the at least one wordline. A programming operation causes the memory cell to change from a first logic state to a second logic state by causing the dielectric region to break down. The programming operation causes the memory cell to operate as a diode. A resistance of the memory cell can be measured in a read operation to determine if the memory cell has the first or second logic state.

    摘要翻译： 根据一个示例性实施例，可编程ROM阵列包括位于衬底中的至少一个位线。 可编程ROM阵列还包括位于至少一个位线上的至少一个字线。 可编程ROM阵列还包括位于所述至少一个位线和所述至少一个字线的交叉点处的存储器单元，其中所述存储器单元包括位于所述至少一个位线和所述至少一个字线之间的电介质区域。 通过使介电区域分解，编程操作使存储单元从第一逻辑状态变为第二逻辑状态。 编程操作使存储单元作为二极管工作。 可以在读取操作中测量存储器单元的电阻，以确定存储单元是否具有第一或第二逻辑状态。

    Flash memory cell and methods for programming and erasing
    19.
    发明授权
    Flash memory cell and methods for programming and erasing 有权
    闪存单元和编程和擦除的方法

    公开(公告)号：US07120063B1

    公开(公告)日：2006-10-10

    申请号：US10841850

    申请日：2004-05-07

    申请人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

    发明人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

    摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

    摘要翻译： 提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。 可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。 电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。 可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池 ，其中栅极电压电位高于衬底电压电位。

    Method and apparatus to facilitate correlating symbols to sounds
    20.
    发明授权
    Method and apparatus to facilitate correlating symbols to sounds 有权
    便于将符号与声音相关联的方法和装置

    公开(公告)号：US06999918B2

    公开(公告)日：2006-02-14

    申请号：US10251354

    申请日：2002-09-20

    申请人： Changxue Ma ,  Mark Randolph

    发明人： Changxue Ma ,  Mark Randolph

    IPC分类号： G10L13/00 ,  G06F17/21

    CPC分类号： G10L13/08

    摘要： A dictionary is comprised of a dendroid hierarchy of branches and nodes, wherein each node represents no more than one symbol (which symbol is to be converted to a corresponding sound) and wherein each such symbol as is represented at a given node has only one corresponding sound associated with that symbol at that node. In addition, many of the branches include a plurality of nodes representing a string of the symbols in a particular sequence. The dictionary is used to translate an input comprising a given integral sequence of the symbols into a corresponding integral sequence of sounds. This permits both method and apparatus to convert, for example, text to representative phonemes. Such phonemes can be used, amongst other purposes, to support synthesized speech production.

    摘要翻译： 字典由分支和节点的树状分层组成，其中每个节点表示不超过一个符号（该符号将被转换为对应的声音），并且其中在给定节点处表示的每个这样的符号只有一个对应 在该节点处与该符号相关联的声音。 此外，许多分支包括表示特定序列中的符号串的多个节点。 字典用于将包括符号的给定整数序列的输入转换成相应的整体声音序列。 这允许方法和装置将例如文本转换为代表性音素。 除了其它目的之外，还可以使用这样的音素来支持合成语音制作。