公开(公告)号：US6162668A

公开(公告)日：2000-12-19

申请号：US260737

申请日：1999-03-03

申请人： Hidekazu Oda ,  Tomohiro Yamashita

发明人： Hidekazu Oda ,  Tomohiro Yamashita

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/762 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/0847 ,  H01L21/28512 ,  H01L21/76216 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7834

摘要： A high withstand voltage semiconductor device includes a semiconductor substrate of a first conductivity type, a metallic wiring formed on a surface of the semiconductor substrate and having a contact face with said semiconductor substrate, a highly doped impurity region formed within the semiconductor substrate below the contact face and of a second conductivity type, a lightly doped impurity region formed around the highly doped impurity region and of the second conductivity type, and a MOSFET with a second conductivity-type having a source or drain region formed on the surface of the semiconductor substrate and electrically connected to the metallic wiring through the impurity regions.

摘要翻译： 高耐压半导体器件包括第一导电类型的半导体衬底，形成在半导体衬底的表面上并具有与所述半导体衬底的接触面的金属布线，形成在半导体衬底下方的高度掺杂杂质区域 面和第二导电类型，形成在高掺杂杂质区域和第二导电类型周围的轻掺杂杂质区域，以及形成在半导体衬底的表面上的具有源极或漏极区域的第二导电类型的MOSFET 并通过杂质区域与金属布线电连接。

公开(公告)号：US6130463A

公开(公告)日：2000-10-10

申请号：US346999

申请日：1999-07-02

申请人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

发明人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/49 ,  H01L21/441

CPC分类号： H01L27/10852 ,  H01L21/28518 ,  H01L27/10894 ,  H01L29/4983 ,  H01L29/66659 ,  H01L27/10873 ,  H01L27/10888

摘要： A silicided region (11a) is formed in part of a surface of a gate electrode (3a) which is far from a storage node when a diffusion region (7a) is connected to a bit line and a diffusion region (8a) is connected to the storage node. A silicided region (12a) is formed in a surface of the diffusion region (7a) connected to the bit line. A MOSFET which suppresses a leakage current from the storage node to the gate electrode and decreases the resistance of the diffusion region connected to the bit line and the resistance of said gate electrode is provided.

公开(公告)号：US06469347B1

公开(公告)日：2002-10-22

申请号：US09553487

申请日：2000-04-20

申请人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

发明人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

IPC分类号： H01L2976

CPC分类号： H01L29/7838 ,  H01L21/761 ,  H01L21/823807 ,  H01L29/1083

摘要： MOS type semiconductor device is formed on the primary surface of a semiconductor substrate. A channel region includes a punch-through stopper layer, a lower counter-doped layer, and an upper counter-doped layer. The punch-through stopper layer is formed between the source region and the drain region and has a first concentration peak. The lower counter-doped layer is formed between the source region and the drain region, and has a second concentration peak at a position shallower than the position of the first concentration peak. Further, the upper counter-doped layer is formed between the source region and the drain region, and has a third concentration peak at a position shallower than the position of the second concentration peak. A buried-channel semiconductor device exhibits high punch-through characteristics and prevents an increase in a threshold voltage.

摘要翻译： MOS半导体器件形成在半导体衬底的主表面上。 沟道区域包括穿通阻止层，下反向掺杂层和上反相掺杂层。 穿通阻止层形成在源极区域和漏极区域之间，并且具有第一浓度峰值。 下部反掺杂层形成在源极区域和漏极区域之间，并且在比第一浓度峰值位置浅的位置处具有第二浓度峰值。 此外，上部反掺杂层形成在源极区域和漏极区域之间，并且在比第二浓度峰值的位置浅的位置处具有第三浓度峰值。 掩埋沟道半导体器件具有高穿透特性并防止阈值电压的增加。

公开(公告)号：US5978294A

公开(公告)日：1999-11-02

申请号：US112506

申请日：1998-07-09

申请人： Shuichi Ueno ,  Tomohiro Yamashita ,  Hidekazu Oda ,  Shigeki Komori

发明人： Shuichi Ueno ,  Tomohiro Yamashita ,  Hidekazu Oda ,  Shigeki Komori

IPC分类号： G01R31/28 ,  G11C7/14 ,  G11C11/401 ,  G11C11/406 ,  G11C29/12 ,  G11C29/24 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/02 ,  G11C11/24

CPC分类号： G11C7/14 ,  G11C11/406 ,  G11C29/24

摘要： A dummy cell part includes a capacitor having a first end which is connected to one of a plurality of pads and a P-N junction element having a first end which is connected to one of the plurality of pads and a second end which is connected to one of the plurality of pads . A sense part is connected to a second end of the capacitor , for sensing a potential on the second end of the capacitor and outputting the result of sensing to one of the plurality of pads . Thus, a memory cell evaluation semiconductor device which can evaluate a single memory cell, a method of fabricating the same and a memory cell evaluation method are obtained.

摘要翻译： 虚设单元部分31包括具有连接到多个焊盘<2>中的一个的第一端的电容器<311>和具有连接到多个焊盘中的一个的第一端的PN结元件<312> 的焊盘<2>和连接到多个焊盘<2>之一的第二端。 感测部分<32>连接到电容器<311>的第二端，用于感测电容器<311>的第二端上的电位，并将感测结果输出到多个焊盘<2>之一。 因此，可以获得能够评估单个存储单元的存储单元评估半导体器件，其制造方法和存储单元评估方法。

公开(公告)号：US5945710A

公开(公告)日：1999-08-31

申请号：US711660

申请日：1996-09-09

申请人： Hidekazu Oda ,  Tomohiro Yamashita

发明人： Hidekazu Oda ,  Tomohiro Yamashita

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L21/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L21/7806 ,  H01L21/76202 ,  H01L21/76879 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/6659

摘要： A high withstand voltage semiconductor device includes a semiconductor substrate of a first conductivity type, a metallic wiring formed on a surface of the semiconductor substrate and having a contact face with said semiconductor substrate, a highly doped impurity region formed within the semiconductor substrate below the contact face and of a second conductivity type, a lightly doped impurity region formed around the highly doped impurity region and of the second conductivity type, and a MOSFET with a second conductivity-type having a source or drain region formed on the surface of the semiconductor substrate and electrically connected to the metallic wiring through the impurity regions.

摘要翻译： 高耐压半导体器件包括第一导电类型的半导体衬底，形成在半导体衬底的表面上并具有与所述半导体衬底的接触面的金属布线，形成在半导体衬底下方的高度掺杂杂质区域 面和第二导电类型，形成在高掺杂杂质区域和第二导电类型周围的轻掺杂杂质区域，以及形成在半导体衬底的表面上的具有源极或漏极区域的第二导电类型的MOSFET 并通过杂质区域与金属布线电连接。

公开(公告)号：US20050202603A1

公开(公告)日：2005-09-15

申请号：US11127093

申请日：2005-05-12

申请人： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

发明人： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/84

CPC分类号： H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

摘要： A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an NMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the NMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the NMOS transistor is enhanced.

摘要翻译： 在硅衬底（10）上设置用于形成NMOS晶体管的非单晶硅的栅极绝缘膜（13）和栅电极（14）。 使用栅电极（14）作为掩模，注入具有较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成NMOS晶体管的源极/漏极区域，由此， 栅电极（14）非晶化。 随后，提供氧化硅膜（40）以比栅电极（14）再结晶发生的温度小的温度覆盖栅电极（14）。 此后，在约1000℃的温度下进行热处理，由此在栅电极（14）上施加高的压缩残余应力，并且对栅电极（14）下的沟道区域施加高的拉伸应力。 结果，增强了NMOS晶体管的载流子迁移率。

公开(公告)号：US6107156A

公开(公告)日：2000-08-22

申请号：US429395

申请日：1999-10-28

申请人： Satoshi Shimizu ,  Hidekazu Oda

发明人： Satoshi Shimizu ,  Hidekazu Oda

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8242

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/32134 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66545 ,  H01L2924/0002 ,  Y10S438/964

摘要： A surface of a conductive member such as a gate electrode provided with a silicon layer is roughened. The roughened silicon layer is silicified so that its width is substantially increased, whereby phase transition of the silicide layer is simplified. Thus, the resistance of the refined silicide layer is reduced due to the simplified phase transition.

摘要翻译： 诸如设置有硅层的栅电极的导电构件的表面被粗糙化。 粗化硅层被硅化，使得其宽度显着增加，从而简化了硅化物层的相变。 因此，由于简化的相变，精制硅化物层的电阻降低。

公开(公告)号：US5710438A

公开(公告)日：1998-01-20

申请号：US550939

申请日：1995-10-31

申请人： Hidekazu Oda ,  Takashi Kuroi

发明人： Hidekazu Oda ,  Takashi Kuroi

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L29/76 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L29/66575 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/456 ,  H01L29/4933

摘要： To form a silicide layer excellent in flatness, uniform in film thickness, and less in junction leak, by destroying the natural oxide film which adversely affects a formation of silicide layer of cobalt or nickel. A cobalt layer (7) is formed in a film thickness of 20 nm or less on an electrode layer (4A) of a gate electrode (4) and on source/drain diffusion layers (1, 2), and a nitrogen (8) is injected by the ion implantation at a density of about 1E15/cm.sup.3 with an injection energy of 10 keV or more. At this time, the nitrogens (8) destroy the natural oxide film existing in the interface of the cobalt layer (7) and electrode layer (4A), and in the interface of the cobalt layer (7) and the source/drain diffusion layers (1, 2), and distribute deeply into the electrode layer (4A) and the source/drain diffusion layers (1, 2). Later, by a silicide forming reaction of cobalt, a silicide layer (6) is formed. Since the natural oxide film does not exist, the silicide forming reaction proceeds uniformly. Instead of the nitrogen (8), fluorine or silicon may be also used.

摘要翻译： 通过破坏对钴或镍的硅化物层的形成有不利影响的自然氧化膜，形成平坦度优异，膜厚均匀，并且漏点较少的硅化物层。 在栅电极（4）的电极层（4A）和源/漏扩散层（1,2）上形成厚度为20nm以下的钴层（7），氮（8） 通过离子注入以约1E15 / cm3的密度注入，注入能量为10keV以上。 此时，氮（8）破坏存在于钴层（7）和电极层（4A）的界面中的自然氧化膜，并且在钴层（7）和源极/漏极扩散层 （1,2），并且深深地分布到电极层（4A）和源极/漏极扩散层（1,2）中。 然后，通过钴的硅化物形成反应，形成硅化物层（6）。 由于天然氧化物膜不存在，所以硅化物形成反应均匀地进行。 代替氮（8），也可以使用氟或硅。

公开(公告)号：US5550409A

公开(公告)日：1996-08-27

申请号：US339662

申请日：1994-11-14

申请人： Takehisa Yamaguchi ,  Hidekazu Oda

发明人： Takehisa Yamaguchi ,  Hidekazu Oda

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L27/1112 ,  H01L23/53257 ,  H01L27/11 ,  H01L2924/0002

摘要： In order to obtain a semiconductor device having an internal wire of low resistance, a conductive layer whose surface is silicified is provided in a surface of a semiconductor substrate. A conductor whose surface is silicified is provided on the semiconductor substrate in proximity to the conductive layer. This semiconductor device is provided with an internal wiring layer, which is formed by a titanium film and a titanium silicide layer for electrically connecting the surface of the conductive layer and a surface of an end of the conductor with each other, to cover a side wall surface and a bottom surface of a contact hole.

摘要翻译： 为了获得具有低电阻的内部线的半导体器件，其表面被硅化的导电层设置在半导体衬底的表面中。 其表面被硅化的导体设置在半导体衬底附近的导电层上。 该半导体器件设置有内部布线层，其由钛膜和钛硅化物层形成，用于将导电层的表面和导体的端部的表面彼此电连接以覆盖侧壁 表面和接触孔的底面。

公开(公告)号：US20110207312A1

公开(公告)日：2011-08-25

申请号：US13103558

申请日：2011-05-09

申请人： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

发明人： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC分类号： H01L21/283

CPC分类号： H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

摘要： A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

摘要翻译： 在硅衬底（10）上设置用于形成nMOS晶体管的非单晶硅的栅极绝缘膜（13）和栅电极（14）。 使用栅极（14）作为掩模，注入具有相对较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此， 栅电极（14）非晶化。 随后，提供氧化硅膜（40）以比栅电极（14）再结晶发生的温度小的温度覆盖栅电极（14）。 此后，在约1000℃的温度下进行热处理，由此在栅电极（14）上施加高的压缩残余应力，并且对栅电极（14）下的沟道区域施加高的拉伸应力。 结果，增强了nMOS晶体管的载流子迁移率。