公开(公告)号：US20050073004A1

公开(公告)日：2005-04-07

申请号：US10929727

申请日：2004-08-31

Applicant: Masahito Onda ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Hiroyasu Ishida

Inventor： Masahito Onda ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Hiroyasu Ishida

IPC: H01L29/06 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/739 ,  H01L29/76 ,  H01L29/78 ,  H01L29/861

CPC classification number: H01L29/7811 ,  H01L29/407 ,  H01L29/7813 ,  Y10S257/908

Abstract: Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.

Abstract translation: 常规的功率MOSFET能够防止围绕元件区域的外围的周围区域由宽的环形层和宽的密封金属引起的反转。 因此，由于周边地区的面积大，元素区域的增加受到限制。 因此提供了具有包含MIS（MOS）结构的反转防止区域的半导体器件。 用于防反转区域的多晶硅的宽度足够大以防止由于沟槽的深度增加氧化膜的面积而导致的反转。 由此，即使围绕元件区域的外周的区域的面积没有扩大，也可以减小泄漏电流。 此外，由于元件区域被扩大，MOSFET的导通电阻可以降低。

公开(公告)号：US20100163922A1

公开(公告)日：2010-07-01

申请号：US12645942

申请日：2009-12-23

Applicant: Shuji Yoneda ,  Hiroyasu Ishida ,  Makoto Oikawa

Inventor： Shuji Yoneda ,  Hiroyasu Ishida ,  Makoto Oikawa

IPC: H01L27/06

CPC classification number: H01L27/0652 ,  H01L29/0696 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/866 ,  H03K17/163

Abstract: By integrating a diode and a resistor connected in parallel into the same chip as an IGBT and connecting a cathode of the diode to a gate of the IGBT, the value of dv/dt can be limited to a predetermined range inside the chip of the IGBT without a deterioration in turn-on characteristics. Since the chip includes a resistor having such a resistance that a dv/dt breakdown of the IGBT can be prevented, the IGBT can be prevented from being broken by an increase in dv/dt at a site (user site) to which the chip is supplied.

Abstract translation: 通过将二极管和电阻并联连接到与IGBT相同的芯片上并将二极管的阴极连接到IGBT的栅极，dv / dt的值可以限制在IGBT的芯片内部的预定范围内 没有导通特性的恶化。 由于芯片包括具有能够防止IGBT的dv / dt击穿的电阻的电阻器，因此可以防止IGBT在芯片的场所（用户现场）处的dv / dt增加而被破坏 提供。

公开(公告)号：US07230300B2

公开(公告)日：2007-06-12

申请号：US10929727

申请日：2004-08-31

Applicant: Masahito Onda ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Hiroyasu Ishida

Inventor： Masahito Onda ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Hiroyasu Ishida

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7811 ,  H01L29/407 ,  H01L29/7813 ,  Y10S257/908

Abstract: Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.

Abstract translation: 常规的功率MOSFET能够防止围绕元件区域的外围的周围区域由宽的环形层和宽的密封金属引起的反转。 因此，由于周边地区的面积大，元素区域的增加受到限制。 因此提供了具有包含MIS（MOS）结构的反转防止区域的半导体器件。 用于防反转区域的多晶硅的宽度足够大以防止由于沟槽的深度增加氧化膜的面积而导致的反转。 由此，即使围绕元件区域的外周的区域的面积没有扩大，也可以减小泄漏电流。 此外，由于元件区域被扩大，MOSFET的导通电阻可以降低。

公开(公告)号：US20060180836A1

公开(公告)日：2006-08-17

申请号：US11355196

申请日：2006-02-16

Applicant: Hiroyasu Ishida ,  Makoto Oikawa ,  Kikuo Okada ,  Shouji Miyahara ,  Naohiro Ochiai ,  Kazunari Kushiyama

Inventor： Hiroyasu Ishida ,  Makoto Oikawa ,  Kikuo Okada ,  Shouji Miyahara ,  Naohiro Ochiai ,  Kazunari Kushiyama

IPC: H01L21/336 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/7802 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7813

Abstract: In the present invention, in a pattern in which gate electrodes are provided in a stripe shape and source regions are provided in a ladder shape, body regions are provided in a stripe shape parallel to the gate electrodes. A first body region is exposed to a surface of a channel layer between first source regions adjacent to the gate electrode, and a second body region is provided below a second source region which connects the first source regions to each other. Thus, avalanche resistance can be improved. Moreover, since a mask for forming the body region is no longer required, there is a margin in accuracy of alignment.

Abstract translation: 在本发明中，在栅电极呈条状而源极区设置为梯状的图案中，以与栅电极平行的条状形成体区。 第一体区域暴露于与栅电极相邻的第一源极区域之间的沟道层的表面，并且第二体区域设置在将第一源极区域彼此连接的第二源极区域的下方。 因此，可以提高雪崩阻力。 此外，由于不再需要用于形成身体区域的掩模，所以对准精度有余量。

公开(公告)号：US08217486B2

公开(公告)日：2012-07-10

申请号：US12236348

申请日：2008-09-23

Applicant: Hiroyasu Ishida ,  Yasuyuki Sayama

Inventor： Hiroyasu Ishida ,  Yasuyuki Sayama

IPC: H01L27/00 ,  H01L21/20

CPC classification number: H01L21/76224 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02439 ,  H01L21/02494 ,  H01L21/02521 ,  H01L21/02573 ,  H01L21/02587 ,  H01L21/02656 ,  H01L21/761 ,  H01L21/764 ,  H01L21/82 ,  H01L21/8222

Abstract: Provided is a semiconductor wafer. In the semiconductor wafer, formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed for at least three times, so that all semiconductor layers are formed of epitaxial layers on a semiconductor substrate. Thereby, the respective semiconductor layers can be formed to have reduced widths. Thus, if a required breakdown voltage is the same, dopant concentrations of the respective semiconductor layers can be increased and a resistance value of the wafer can be reduced. In addition, a space portion remaining in the end is buried with an insulating layer, so that a defect can be avoided in a junction surface of the epitaxial layers.

Abstract translation: 提供半导体晶片。 在半导体晶片中，n型外延层的形成和蚀刻以及p型外延层的形成和蚀刻被交替执行至少三次，使得所有半导体层由半导体衬底上的外延层形成。 由此，各个半导体层可以形成为具有减小的宽度。 因此，如果所需的击穿电压相同，则可以增加各个半导体层的掺杂剂浓度，并且可以降低晶片的电阻值。 此外，剩余的空间部分被绝缘层掩埋，使得在外延层的接合表面中可以避免缺陷。

公开(公告)号：US20100015772A1

公开(公告)日：2010-01-21

申请号：US12567050

申请日：2009-09-25

Applicant: Yasuyuki SAYAMA ,  Tetsuya Okada ,  Makoto Oikawa ,  Hiroyasu Ishida ,  Kazunari Kushiyama

Inventor： Yasuyuki SAYAMA ,  Tetsuya Okada ,  Makoto Oikawa ,  Hiroyasu Ishida ,  Kazunari Kushiyama

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66712

Abstract: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.

Abstract translation: 在栅电极的下方设置有n型杂质区。 通过将栅极长度设置为小于沟道区的深度，沟道区的侧表面和与沟道区相邻的n型杂质区的侧表面形成基本上垂直的接合表面。 因此，由于耗尽层在衬底的深度方向上均匀地变宽，因此可以确保预定的击穿电压。 此外，由于栅极电极上方的沟道区域之间的间隔从表面到底部均匀，所以可以增加n型杂质区域的杂质浓度，导致实现低的导通 -抵抗性。

公开(公告)号：US20090085149A1

公开(公告)日：2009-04-02

申请号：US12236348

申请日：2008-09-23

Applicant: Hiroyasu Ishida ,  Yasuyuki Sayama

Inventor： Hiroyasu Ishida ,  Yasuyuki Sayama

IPC: H01L27/00 ,  H01L21/20

CPC classification number: H01L21/76224 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02439 ,  H01L21/02494 ,  H01L21/02521 ,  H01L21/02573 ,  H01L21/02587 ,  H01L21/02656 ,  H01L21/761 ,  H01L21/764 ,  H01L21/82 ,  H01L21/8222

Abstract: Provided is a semiconductor wafer. In the semiconductor wafer, formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed for at least three times, so that all semiconductor layers are formed of epitaxial layers on a semiconductor substrate. Thereby, the respective semiconductor layers can be formed to have reduced widths. Thus, if a required breakdown voltage is the same, dopant concentrations of the respective semiconductor layers can be increased and a resistance value of the wafer can be reduced. In addition, a space portion remaining in the end is buried with an insulating layer, so that a defect can be avoided in a junction surface of the epitaxial layers.

Abstract translation: 提供半导体晶片。 在半导体晶片中，n型外延层的形成和蚀刻以及p型外延层的形成和蚀刻被交替执行至少三次，使得所有半导体层由半导体衬底上的外延层形成。 由此，各个半导体层可以形成为具有减小的宽度。 因此，如果所需的击穿电压相同，则可以增加各个半导体层的掺杂剂浓度，并且可以降低晶片的电阻值。 此外，剩余的空间部分被绝缘层掩埋，使得在外延层的接合表面中可以避免缺陷。

公开(公告)号：US07439137B2

公开(公告)日：2008-10-21

申请号：US11123248

申请日：2005-05-06

Applicant: Hiroyasu Ishida ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Masato Onda

Inventor： Hiroyasu Ishida ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Masato Onda

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/3003 ,  H01L21/76886 ,  H01L21/823487 ,  H01L29/456

Abstract: In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the barrier metal layer. Thus, an increased impurity concentration in a channel layer causes a problem that reduction in an on-resistance is inhibited. According to the present invention, after a barrier metal layer is formed, an opening is provided in the barrier metal layer on an interlayer insulating film, and hydrogen annealing treatment is performed after a wiring layer is formed. Thus, an amount of hydrogen which reaches a substrate is further increased, and lowering of a threshold voltage is suppressed. Moreover, since an impurity concentration in a channel layer can be lowered, an on-resistance is reduced.

Abstract translation: 在MOSFET中，在形成元件区之后，在阻挡金属层的后面形成布线层，进行氢退火。 然而，在n沟道MOSFET的情况下，由于阻挡金属层的遮挡特性，阈值电压降低。 因此，通道层中杂质浓度的增加引起导通电阻的降低被抑制的问题。 根据本发明，在形成阻挡金属层之后，在层间绝缘膜上的阻挡金属层中设置开口，在形成布线层之后进行氢退火处理。 因此，到达基板的氢的量进一步增加，并且抑制了阈值电压的降低。 此外，由于可以降低沟道层中的杂质浓度，所以导通电阻降低。

公开(公告)号：US20070072352A1

公开(公告)日：2007-03-29

申请号：US11519208

申请日：2006-09-12

Applicant: Kazunari Kushiyama ,  Tetsuya Okada ,  Makoto Oikawa ,  Hiroyasu Ishida ,  Yasuyuki Sayama

Inventor： Kazunari Kushiyama ,  Tetsuya Okada ,  Makoto Oikawa ,  Hiroyasu Ishida ,  Yasuyuki Sayama

IPC: H01L21/337 ,  H01L21/8242 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/66727

Abstract: A separation hole is provided in the center of the gate electrode. Accordingly, it is possible to suppress a drastic increase in feedback capacitance Crss in the case where drain-source voltage VDS is decreased and the width of the depletion layer is narrowed. Thus, high-frequency switching characteristics are improved. Moreover, n type impurities are implanted from the separation hole to form an n type impurity region between channel regions. Since a resistance in a portion below the gate electrode can be reduced, an on-resistance can be reduced. The n type impurity region can be formed in a self-aligning manner.

Abstract translation: 在栅电极的中心设置有分离孔。 因此，在漏极 - 源极电压VDS降低并且耗尽层的宽度变窄的情况下，可以抑制反馈电容Crss急剧增加。 因此，提高了高频开关特性。 此外，从分离孔注入n型杂质，在沟道区域之间形成n型杂质区。 由于可以减小栅电极下方的电阻，所以可以降低导通电阻。 可以以自对准的方式形成n型杂质区域。

公开(公告)号：US20070007588A1

公开(公告)日：2007-01-11

申请号：US11471733

申请日：2006-06-21

Applicant: Hiroyasu Ishida ,  Tadao Mandai ,  Atsuya Ushida ,  Hiroaki Saito

Inventor： Hiroyasu Ishida ,  Tadao Mandai ,  Atsuya Ushida ,  Hiroaki Saito

IPC: H01L29/94 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/66734

Abstract: A first electrode layer, which comes into contact with a source region, and a second electrode layer, which comes into contact with a body (back gate) region, are provided. The first and second electrode layers are insulated from each other and are extended in a direction different from an extending direction of a trench. It is possible to individually apply potentials to the first and second electrode layers, and to perform control for preventing a reverse current caused by a parasitic diode. Therefore, a bidirectional switching element can be realized by use of one MOSFET.

Abstract translation: 设置与源极区域接触的第一电极层和与主体（背栅极）区域接触的第二电极层。 第一和第二电极层彼此绝缘并且沿与沟槽的延伸方向不同的方向延伸。 可以分别对第一和第二电极层施加电位，并且执行用于防止由寄生二极管引起的反向电流的控制。 因此，可以通过使用一个MOSFET来实现双向开关元件。