公开(公告)号：US20080253184A1

公开(公告)日：2008-10-16

申请号：US11868342

申请日：2007-10-05

Applicant: Ryotaro SAKURAI ,  Hitoshi Tanaka ,  Satoshi Noda ,  Koji Shigematsu

Inventor： Ryotaro SAKURAI ,  Hitoshi Tanaka ,  Satoshi Noda ,  Koji Shigematsu

IPC: G11C16/06

CPC classification number: G11C16/3409 ,  G11C11/5621 ,  G11C16/225 ,  G11C16/30 ,  G11C16/3404

Abstract: An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.

Abstract translation: 一种电可编程和可擦除的非易失性半导体存储器，例如闪速存储器被设计成这样的配置，其中当在非非易失性存储器中使用的存储器单元执行写入或擦除操作的过程中发生电源的截止时， 不稳定的半导体存储器，中断正在执行的操作，并且执行回写操作以改变存储单元在相反方向上的阈值电压。 此外，该配置还允许根据电源电压的电平来改变内部电源配置中的电荷泵级数，以使回写操作正确执行。 结果，即使在写入或擦除操作的过程中电源断开的情况下，也不会将存储器单元置于耗尽状态。

公开(公告)号：US07437645B2

公开(公告)日：2008-10-14

申请号：US11709786

申请日：2007-02-23

Applicant: Hiroyuki Fukuyama ,  Takeru Yonaga ,  Hitoshi Tanaka

Inventor： Hiroyuki Fukuyama ,  Takeru Yonaga ,  Hitoshi Tanaka

IPC: G01R31/28

CPC classification number: G11C29/30 ,  G11C2029/0405 ,  G11C2029/3202

Abstract: A semiconductor test circuit includes an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives a serial data including a command code and a control data. The controller receives a control signal and outputs an internal control signal based on the control signal. The setting circuit receives the serial data and outputs it in response to the internal control signal. The command generator generates an interface signal based on the serial data received from the setting circuit. The switching circuit has ports, receives the signal from one of the ports and outputs the received signal to another one of the ports in response to the internal control signal and the command code. The comparator compares the interface signal received from the command generator with the signal received from the switching circuit.

Abstract translation: 半导体测试电路包括输入端子，控制器，设置电路，命令发生器，传输路径切换电路和比较器。 输入端子接收包括命令码和控制数据的串行数据。 控制器接收控制信号，并根据控制信号输出内部控制信号。 设置电路接收串行数据并根据内部控制信号输出。 命令发生器基于从设置电路接收的串行数据生成接口信号。 开关电路具有端口，从一个端口接收信号，并响应于内部控制信号和命令码将接收的信号输出到另一个端口。 比较器将从命令发生器接收的接口信号与从开关电路接收的信号进行比较。

公开(公告)号：US20080238605A1

公开(公告)日：2008-10-02

申请号：US12076922

申请日：2008-03-25

Applicant: Naoyoshi Yoshida ,  Hitoshi Tanaka ,  Dai Matsuoka

Inventor： Naoyoshi Yoshida ,  Hitoshi Tanaka ,  Dai Matsuoka

IPC: H01C7/10

CPC classification number: H01C7/1006 ,  H01C7/112 ,  H01C7/18

Abstract: As for the voltage non-linear resistance element layer 2, sintered body (ceramics) having ZnO as main component is used. Said sintered body comprises Pr, Co, Ca and Na are added. Therefore, the ranges are 0.05 to 5.0 atm % of Pr, 0.1 to 20 atm % of Co, 0.01 to 5.0 atm % of Ca and 0.0001 to 0.0008 atm % of Na. When it is within the range, the capacitance changing rate at 85° C. with standard being 25° C. can be made to equal or less than 10%.

Abstract translation: 对于电压非线性电阻元件层2，使用以ZnO为主要成分的烧结体（陶瓷）。 所述烧结体包括Pr，Co，Ca和Na。 因此，Pr为0.05〜5.0atm％，Co为0.1〜20atm％，Ca为0.01〜5.0atm％，Na为0.0001〜0.0008atm。 当在该范围内时，可以将标准为25℃的85℃下的电容变化率设为等于或小于10％。

公开(公告)号：US20080233705A1

公开(公告)日：2008-09-25

申请号：US11688684

申请日：2007-03-20

Applicant: Eiichi Kondoh ,  Michiru Hirose ,  Hitoshi Tanaka ,  Masayuki Satoh ,  Hisashi Yano ,  Masaki Yoshimaru

Inventor： Eiichi Kondoh ,  Michiru Hirose ,  Hitoshi Tanaka ,  Masayuki Satoh ,  Hisashi Yano ,  Masaki Yoshimaru

IPC: H01L21/20

CPC classification number: H01L21/76879 ,  C23C18/1216 ,  C23C18/1279 ,  C23C18/1283 ,  H01L21/288 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for selectively forming an electric conductor, the method including disposing a processing target and a metal compound in an atmosphere including a supercritical fluid, the processing target having formed thereon at least one recess for providing an electric conductor, the metal compound including a metal serving as a main component of the electric conductor, and dissolving at least part of the metal compound in the supercritical fluid, selectively introducing the metal compound dissolved in the supercritical fluid into the recess in contact with a surface of the processing target, and coagulating in the recess the metal compound introduced into the recess to precipitate the metal from the metal compound, and coagulating the metal precipitated in the recess, thereby providing the electric conductor in the recess.

Abstract translation: 一种用于选择性地形成电导体的方法，所述方法包括在包括超临界流体的气氛中设置处理对象和金属化合物，所述处理对象在其上形成有至少一个用于提供导电体的凹部，所述金属化合物包括金属 作为电导体的主要成分，将至少一部分金属化合物溶解在超临界流体中，选择性地将溶解在超临界流体中的金属化合物导入到与加工对象的表面接触的凹部中， 所述金属化合物引入所述凹部中以将所述金属从所述金属化合物中沉淀出来并将所述金属凝结在所述凹部中沉淀，由此在所述凹部中提供所述电导体。

公开(公告)号：US07426136B2

公开(公告)日：2008-09-16

申请号：US11130274

申请日：2005-05-17

Applicant: Ryotaro Sakurai ,  Hitoshi Tanaka ,  Satoshi Noda ,  Koji Shigematsu

Inventor： Ryotaro Sakurai ,  Hitoshi Tanaka ,  Satoshi Noda ,  Koji Shigematsu

IPC: G11C16/30

CPC classification number: G11C16/3409 ,  G11C11/5621 ,  G11C16/225 ,  G11C16/30 ,  G11C16/3404

Abstract: An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.

Abstract translation: 一种电可编程和可擦除的非易失性半导体存储器，例如闪速存储器被设计成这样的配置，其中当在非非易失性存储器中使用的存储器单元执行写入或擦除操作的过程中发生电源的截止时， 不稳定的半导体存储器，中断正在执行的操作，并且执行回写操作以改变存储单元在相反方向上的阈值电压。 此外，该配置还允许根据电源电压的电平来改变内部电源配置中的电荷泵级数，以使回写操作正确执行。 结果，即使在写入或擦除操作的过程中电源断开的情况下，也不会将存储器单元置于耗尽状态。

公开(公告)号：US20080059110A1

公开(公告)日：2008-03-06

申请号：US11896295

申请日：2007-08-30

Applicant: Hiroki Fujisawa ,  Hitoshi Tanaka ,  Atsuo Koshizuka

Inventor： Hiroki Fujisawa ,  Hitoshi Tanaka ,  Atsuo Koshizuka

IPC: G01K1/00

CPC classification number: G01K7/015 ,  G01K2219/00

Abstract: A semiconductor integrated circuit includes a temperature detecting unit that detects the temperature of a chip, and an A/D converter that converts an analog output VBE from the temperature detecting unit into a digital output. The A/D converter includes an up/down counter, a D/A converter that converts an output T2 from the up/down counter into an analog output, and a comparator that compares the analog output DAC_OUT of the D/A converter and the analog output VBE (VTEMP) of the temperature detecting unit. The up/down counter is adapted to be able to preset an initial value that is different from the minimum value or the maximum value. Accordingly, the determination time required at the initial conversion can be reduced although the linear search method is used.

Abstract translation: 半导体集成电路包括检测芯片的温度的温度检测单元和将来自温度检测单元的模拟输出VBE转换为数字输出的A / D转换器。 A / D转换器包括一个向上/向下计数器，一个将输出T 2从上/下计数器转换为模拟输出的D / A转换器，以及比较器，用于将D / A转换器的模拟输出DAC_OUT和 温度检测单元的模拟输出VBE（VTEMP）。 上/下计数器适于能够预设不同于最小值或最大值的初始值。 因此，尽管使用线性搜索方法，但是可以减少初始转换所需的确定时间。

公开(公告)号：US07307909B2

公开(公告)日：2007-12-11

申请号：US11297646

申请日：2005-12-09

Applicant: Yoshinori Matsui ,  Hitoshi Tanaka ,  Kazuhiko Kajigaya ,  Akiyoshi Yamamoto ,  Tadashi Onodera

Inventor： Yoshinori Matsui ,  Hitoshi Tanaka ,  Kazuhiko Kajigaya ,  Akiyoshi Yamamoto ,  Tadashi Onodera

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G11C11/40615

Abstract: A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.

Abstract translation: 一种自刷新定时器电路，用于产生用于控制半导体存储器件的自刷新操作的定时器周期，包括：用于输出基于二极管特性的具有温度依赖性的电压的温度相关电压源; 控制电流产生电路，用于将温度依赖电压源的输出电压施加到具有二极管特性的温度检测装置，并产生与流过温度检测装置的电流成比例的控制电流; 以及定时器周期发生电路，用于产生与控制电流的大小成反比的定时器周期。

公开(公告)号：US20070223170A1

公开(公告)日：2007-09-27

申请号：US11717098

申请日：2007-03-13

Applicant: Hiroyuki Sato ,  Yo Saito ,  Hitoshi Tanaka ,  Makoto Numata ,  Goro Takeuchi

Inventor： Hiroyuki Sato ,  Yo Saito ,  Hitoshi Tanaka ,  Makoto Numata ,  Goro Takeuchi

IPC: H02H9/06

CPC classification number: H01C7/102 ,  H01C1/142 ,  H01L25/167 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225

Abstract: A varistor comprises an element body, two external electrodes, and a metal conductor. The element body includes a portion having first and second faces opposing each other. Two external electrodes are arranged on the first face of the element body. The metal conductor is arranged on the second face of the element body. The metal conductor has a thermal conductivity higher than that of the element body. At least a region between the two external electrodes and metal conductor in the element body exhibits a nonlinear current-voltage characteristic. The heat transmitted to the varistor is efficiently diffused from the metal conductor in the varistor.

Abstract translation: 变阻器包括元件体，两个外部电极和金属导体。 元件主体包括具有彼此相对的第一和第二面的部分。 两个外部电极布置在元件主体的第一面上。 金属导体布置在元件主体的第二面上。 金属导体的导热系数高于元件体的导热系数。 元件体内的至少两个外部电极和金属导体之间的区域呈现非线性电流 - 电压特性。 传输到变阻器的热量有效地从压敏电阻中的金属导体扩散。

公开(公告)号：US20070208966A1

公开(公告)日：2007-09-06

申请号：US11709786

申请日：2007-02-23

Applicant: Hiroyuki Fukuyama ,  Takeru Yonaga ,  Hitoshi Tanaka

Inventor： Hiroyuki Fukuyama ,  Takeru Yonaga ,  Hitoshi Tanaka

IPC: G06K5/04

CPC classification number: G11C29/30 ,  G11C2029/0405 ,  G11C2029/3202

Abstract: A semiconductor test circuit includes an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives a serial data including a command code and a control data. The controller receives a control signal and outputs an internal control signal based on the control signal. The setting circuit receives the serial data and outputs it in response to the internal control signal. The command generator generates an interface signal based on the serial data received from the setting circuit. The switching circuit has ports, receives the signal from one of the ports and outputs the received signal to another one of the ports in response to the internal control signal and the command code. The comparator compares the interface signal received from the command generator with the signal received from the switching circuit.

Abstract translation: 半导体测试电路包括输入端子，控制器，设置电路，命令发生器，传输路径切换电路和比较器。 输入端子接收包括命令码和控制数据的串行数据。 控制器接收控制信号，并根据控制信号输出内部控制信号。 设置电路接收串行数据并根据内部控制信号输出。 命令发生器基于从设置电路接收的串行数据生成接口信号。 开关电路具有端口，从一个端口接收信号，并响应于内部控制信号和命令码将接收的信号输出到另一个端口。 比较器将从命令发生器接收的接口信号与从开关电路接收的信号进行比较。

公开(公告)号：US20060049084A1

公开(公告)日：2006-03-09

申请号：US11213897

申请日：2005-08-30

Applicant: Fuminori Suzuki ,  Hitoshi Tanaka

Inventor： Fuminori Suzuki ,  Hitoshi Tanaka

IPC: B01D35/143

CPC classification number: G05D7/0635 ,  F16H61/0009 ,  Y10T137/8326 ,  Y10T477/60

Abstract: A fluid circuit module controls a fluid to be supplied to a movable element in an automatic transmission. The fluid circuit module is provided with a first body in which a first flow passage is formed, a second body in which a second flow passage is formed. A separation plate is set between the first body and the second body and has a deformation portion that is deformed and strained in accordance with the difference between pressures in the first flow passage and the second flow passage. A strain sensor is attached to the deformation portion for detecting a strain of the deformation portion. A control means controls a supply fluid to be supplied to the movable element on the basis of a detection result of the strain sensor.