公开(公告)号：US08097901B2

公开(公告)日：2012-01-17

申请号：US13115137

申请日：2011-05-25

申请人： Masaki Koyama ,  Yoshifumi Okabe ,  Makoto Asai ,  Takeshi Fujii ,  Koh Yoshikawa

发明人： Masaki Koyama ,  Yoshifumi Okabe ,  Makoto Asai ,  Takeshi Fujii ,  Koh Yoshikawa

IPC分类号： H01L29/739

CPC分类号： H01L29/7395 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/7397

摘要： A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.

摘要翻译： 具有IGBT的半导体器件包括：基板; 衬底上的漂移层和基底层; 穿过基层的沟槽将基层分成基部; 一个基部的发射极区域; 沟槽中的栅极元件; 发射极; 和集电极。 一个基座部分提供通道层，而另一个基座部件提供没有发射极区域的浮动层。 栅极元件包括靠近沟道层的栅极电极和与浮置层相邻的伪栅极电极。 浮子层包括与沟道层相邻的第一浮动层和与沟道层分开的第二浮体层。 虚拟栅电极和第一浮动层与基层上的第一浮动布线耦合。 虚拟栅电极与第二浮动层隔离。

公开(公告)号：US07838331B2

公开(公告)日：2010-11-23

申请号：US11598654

申请日：2006-11-14

申请人： Atsushi Komura ,  Tetsuo Fujii ,  Muneo Tamura ,  Makoto Asai

发明人： Atsushi Komura ,  Tetsuo Fujii ,  Muneo Tamura ,  Makoto Asai

IPC分类号： H01L21/00

CPC分类号： H01L21/67132 ,  B23K26/009 ,  B23K26/40 ,  B23K26/53 ,  B23K2101/40 ,  B23K2103/50 ,  B28D5/0011 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3192 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： A device separated from a wafer includes: a chip having a sidewall, which is provided by a dicing surface of the wafer in a case where the device is separated from the wafer; and a protection member disposed on the sidewall of the chip for protecting the chip from being contaminated by a dust from the dicing surface. In the device, the dicing surface of the wafer is covered with the protection member so that the chip is prevented from contaminated with the dust.

摘要翻译： 与晶片分离的器件包括：具有侧壁的芯片，其在器件与晶片分离的情况下由晶片的切割表面提供; 以及设置在芯片的侧壁上的保护构件，用于保护芯片免受来自切割表面的灰尘的污染。 在该装置中，晶片的切割面被保护部件覆盖，从而防止芯片被灰尘污染。

公开(公告)号：US20090189181A1

公开(公告)日：2009-07-30

申请号：US12320497

申请日：2009-01-27

申请人： Masaki Koyama ,  Yoshifumi Okabe ,  Makoto Asai ,  Takeshi Fujii ,  Koh Yoshikawa

发明人： Masaki Koyama ,  Yoshifumi Okabe ,  Makoto Asai ,  Takeshi Fujii ,  Koh Yoshikawa

IPC分类号： H01L29/739

CPC分类号： H01L29/7395 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/7397

摘要： A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.

摘要翻译： 具有IGBT的半导体器件包括：基板; 衬底上的漂移层和基底层; 穿过基层的沟槽将基层分成基部; 一个基部的发射极区域; 沟槽中的栅极元件; 发射极; 和集电极。 一个基座部分提供通道层，而另一个基座部件提供没有发射极区域的浮动层。 栅极元件包括靠近沟道层的栅极电极和与浮置层相邻的伪栅极电极。 浮子层包括与沟道层相邻的第一浮动层和与沟道层分开的第二浮体层。 虚拟栅电极和第一浮动层与基层上的第一浮动布线耦合。 虚拟栅电极与第二浮动层隔离。

公开(公告)号：US07326586B2

公开(公告)日：2008-02-05

申请号：US11172787

申请日：2005-07-05

申请人： Makoto Asai

发明人： Makoto Asai

IPC分类号： H01L21/00

CPC分类号： B81C1/00142 ,  B81B2201/0292 ,  B81B2203/0118 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814

摘要： A method for manufacturing a semiconductor physical quantity sensor is provided. The sensor includes a multi-layered substrate, a cavity, a groove, a movable portion and a fixed portion. The multi-layered substrate includes a support substrate, an embedded insulation film, and a semiconductor layer. The method includes the steps of: preparing the multi-layered substrate having a sacrifice layer embedded in the semiconductor layer so that the sacrifice layer is disposed at a cavity-to-be-formed portion; forming the groove from the semiconductor layer to reach the sacrifice layer; and selectively etching the sacrifice layer from a bottom of the groove to form a cavity.

摘要翻译： 提供一种半导体物理量传感器的制造方法。 传感器包括多层基板，空腔，凹槽，可移动部分和固定部分。 多层基板包括支撑基板，嵌入式绝缘膜和半导体层。 该方法包括以下步骤：制备具有嵌入在半导体层中的牺牲层的多层基板，使得牺牲层设置在待形成腔部分; 从半导体层形成凹槽到达牺牲层; 并且从凹槽的底部选择性地蚀刻牺牲层以形成空腔。

公开(公告)号：US20080009090A1

公开(公告)日：2008-01-10

申请号：US11896171

申请日：2007-08-30

申请人： Makoto Asai

发明人： Makoto Asai

IPC分类号： H01L21/306

CPC分类号： B81C1/00626 ,  B81B2201/0235 ,  B81B2201/0292 ,  B81B2203/0118 ,  B81C2201/014 ,  B81C2201/019 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814

摘要： A physical quantity sensor includes: a semiconductor substrate; a cavity disposed in the substrate and extending in a horizontal direction of the substrate; a groove disposed on the substrate and reaching the cavity; a movable portion separated by the cavity and the groove so that the movable portion is movably supported on the substrate; and an insulation layer disposed on a bottom of the movable portion so that the insulation layer provides a roof of the cavity.

摘要翻译： 物理量传感器包括：半导体衬底; 设置在所述基板中并在所述基板的水平方向上延伸的空腔; 设置在所述基板上并到达所述空腔的凹槽; 可移动部分，由空腔和沟槽分隔开，使得可移动部分可移动地支撑在基板上; 以及设置在所述可动部分的底部上的绝缘层，使得所述绝缘层提供所述空腔的顶部。

公开(公告)号：US20070111476A1

公开(公告)日：2007-05-17

申请号：US11591496

申请日：2006-11-02

申请人： Kazuhiko Sugiura ,  Kenichi Yokoyama ,  Muneo Tamura ,  Tetsuo Fujii ,  Makoto Asai

发明人： Kazuhiko Sugiura ,  Kenichi Yokoyama ,  Muneo Tamura ,  Tetsuo Fujii ,  Makoto Asai

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  B23K26/16 ,  B23K26/40 ,  B23K26/53 ,  B23K2101/40 ,  B23K2103/50 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2924/3025

摘要： A separating device for separating a semiconductor substrate includes: a cutting element for cutting the semiconductor substrate into a plurality of chips along with a cutting line on the semiconductor substrate; an adsorbing element for adsorbing a dust on a surface of the semiconductor substrate by using electrostatic force; and a static electricity generating element for generating static electricity and for controlling the static electricity in order to remove the dust from the adsorbing element.

摘要翻译： 用于分离半导体衬底的分离装置包括：用于将半导体衬底与半导体衬底上的切割线一起切割成多个芯片的切割元件; 用于通过使用静电力吸附在所述半导体衬底的表面上的灰尘的吸附元件; 以及用于产生静电并用于控制静电以便从吸附元件去除灰尘的静电发生元件。

公开(公告)号：US07178400B2

公开(公告)日：2007-02-20

申请号：US11095469

申请日：2005-04-01

申请人： Minoru Murata ,  Kenichi Yokoyama ,  Makoto Asai

发明人： Minoru Murata ,  Kenichi Yokoyama ,  Makoto Asai

IPC分类号： G01P15/00 ,  G01P15/125

CPC分类号： G01C19/5719 ,  G01P15/125

摘要： A semiconductor physical quantity sensor includes: a substrate; a semiconductor layer supported on the substrate; a trench disposed in the semiconductor layer; and a movable portion disposed in the semiconductor layer and separated from the substrate by the trench. The movable portion includes a plurality of through-holes, each of which penetrates the semiconductor layer in a thickness direction. The movable portion is capable of displacing on the basis of a physical quantity applied to the movable portion so that the physical quantity is detected by a displacement of the movable portion. The movable portion has a junction disposed among the through-holes. The junction has a trifurcate shape.

公开(公告)号：US20060273324A1

公开(公告)日：2006-12-07

申请号：US10566211

申请日：2004-07-26

申请人： Makoto Asai ,  Shiro Yamazaki ,  Takahiro Kozawa ,  Mitsuhisa Narukawa

发明人： Makoto Asai ,  Shiro Yamazaki ,  Takahiro Kozawa ,  Mitsuhisa Narukawa

IPC分类号： H01L21/00 ,  H01L33/00

CPC分类号： H01L33/20 ,  H01L24/32 ,  H01L33/32 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2924/10158 ,  H01L2924/00014 ,  H01L2924/00

摘要： The back surface of a semiconductor crystal substrate 102 which has a thickness of about 150 μm and is made of undoped GaN bulk crystal consists of a polished plane 102a which is flattened through dry-etching and a grinded plane 102b which is formed in a taper shape and is flattened through dry-etching. On about 10 nm in thickness of GaN n-type clad layer (low carrier concentration layer) 104, about 2 nm in thickness of Al0.005In0.045Ga0.95N well layer 51 and about 18 nm in thickness of Al0.12Ga0.88N barrier layer 52 are deposited alternately as an active layer 105 which emits ultraviolet light and has MQW structure comprising 5 layers in total. Before forming a negative electrode (n-electrode c) on the polished plane of the semiconductor substrate a, the polished plane is dry-etched.

摘要翻译： 半导体晶体基板102的背面，其厚度为约150μm，由未掺杂的GaN体晶体制成，其由经干蚀刻而平坦化的抛光平面102a和形成在其中的研磨平面102b 锥形，并通过干蚀刻变平。 在GaN n型覆层（低载流子浓度层）104的厚度约为10nm的情况下，厚度为约0.01nm的Al 0.005 In 0.95 Ga 0.95 N阱层51和厚度约为18nm的Al 0.12 N Ga 0.88 N阻挡层52交替地沉积为发射紫外光的有源层105和 总共有5层MQW结构。 在半导体衬底a的抛光平面上形成负电极（n电极c）之前，对该抛光平面进行干式蚀刻。

公开(公告)号：US20060220183A1

公开(公告)日：2006-10-05

申请号：US11392739

申请日：2006-03-30

申请人： Makoto Asai ,  Muneo Tamura ,  Kazuhiko Sugiura ,  Tetsuo Fujii

发明人： Makoto Asai ,  Muneo Tamura ,  Kazuhiko Sugiura ,  Tetsuo Fujii

IPC分类号： H01L29/06 ,  H01L21/00

CPC分类号： H01L21/67132 ,  H01L21/78

摘要： A semiconductor wafer includes: a first layer having a first refraction index; a second layer having a second refraction index, which is different from the first refraction index; a plurality of semiconductor elements; and a layer removal region. The semiconductor elements are capable of being separated each other by irradiating a laser beam on the first layer along with a cutting line. The laser beam irradiation provides a modified region in the first layer so that the semiconductor elements are capable of being separated by a crack generated in the modified region. The layer removal region is provided such that the second layer in the layer removal region is removed from the wafer.

摘要翻译： 半导体晶片包括：具有第一折射率的第一层; 具有与第一折射率不同的第二折射率的第二层; 多个半导体元件; 和层去除区域。 半导体元件能够通过与切割线一起照射第一层上的激光束而彼此分离。 激光束照射在第一层中提供改性区域，使得半导体元件能够被改性区域中产生的裂纹分离。 提供了去除层，使得去除层中的第二层从晶片上去除。

公开(公告)号：US07018915B2

公开(公告)日：2006-03-28

申请号：US10860035

申请日：2004-06-04

申请人： Naoki Shibata ,  Toshiya Uemura ,  Makoto Asai ,  Yasuo Koide ,  Masanori Murakami

发明人： Naoki Shibata ,  Toshiya Uemura ,  Makoto Asai ,  Yasuo Koide ,  Masanori Murakami

IPC分类号： H01L21/28 ,  H01L33/00

CPC分类号： H01L33/40 ,  H01L21/242 ,  H01L21/28575 ,  H01L33/0095 ,  H01L33/06 ,  H01L33/32 ,  H01S5/0213 ,  H01S5/32341

摘要： An AlN buffer layer 2; a silicon (Si)-doped GaN high-carrier-concentration n+ layer 3; an Si-doped n-type Al0.07Ga0.93N n-cladding layer 4; an Si-doped n-type GaN n-guide layer 5; an active layer 6 having a multiple quantum well (MQW) structure, and including a Ga0.9In0.1N well layer 61 (thickness: about 2 nm) and a Ga0.97In0.03N barrier layer 62 (thickness: about 4 nm), the layers 61 and 62 being laminated alternately; an Mg-doped GaN p-guide layer 7; an Mg-doped Al0.07Ga0.93N p-cladding layer 8; and an Mg-doped GaN p-contact layer 9 are successively formed on a sapphire substrate. A p-electrode 10 is formed of a film of titanium nitride (TiN) or tantalum nitride (TaN) (thickness: 50 nm). The contact resistance of this electrode is reduced through heat treatment.

摘要翻译： AlN缓冲层2; 硅（Si）掺杂的GaN高载流子浓度的n + 3层3; Si掺杂的n型Al 0.07 N 0.93 N n包覆层4; Si掺杂的n型GaN n引导层5; 具有多重量子阱（MQW）结构的有源层6，并且包括Ga 0.1 N 1 In 0.1 N阱层61（厚度：约2nm）和Ga < SUB> 0.97在0.03N阻挡层62（厚度：约4nm）中，层61和62交替层叠; Mg掺杂的GaN p引导层7; Mg掺杂的Al 0.07 N 0.93 N p包层8; 并且在蓝宝石衬底上依次形成Mg掺杂的GaN p接触层9。 p电极10由氮化钛（TiN）或氮化钽（TaN）（厚度：50nm）的膜形成。 该电极的接触电阻通过热处理而降低。