公开(公告)号：US20230369399A1

公开(公告)日：2023-11-16

申请号：US18225440

申请日：2023-07-24

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Anh PHAN ,  Aaron LILAK ,  Willy RACHMADY ,  Gilbert DEWEY ,  Cheng-Ying HUANG ,  Richard SCHENKER ,  Hui Jae YOO ,  Patrick MORROW

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/068 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.

公开(公告)号：US20220102246A1

公开(公告)日：2022-03-31

申请号：US17547066

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Anh PHAN ,  Patrick MORROW ,  Stephanie A. BOJARSKI

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/088

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer.

公开(公告)号：US20210057413A1

公开(公告)日：2021-02-25

申请号：US16954126

申请日：2018-03-28

Applicant: Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Intel Corporation

Inventor： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ

IPC: H01L27/092 ,  H01L21/822 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US20200219979A1

公开(公告)日：2020-07-09

申请号：US16240369

申请日：2019-01-04

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Aaron LILAK ,  Patrick MORROW ,  Anh PHAN ,  Cheng-Ying HUANG ,  Ehren MANNEBACH

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.

公开(公告)号：US20200006388A1

公开(公告)日：2020-01-02

申请号：US16024696

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Patrick MORROW ,  Aaron LILAK ,  Willy RACHMADY ,  Anh PHAN ,  Ehren MANNEBACH ,  Hui Jae YOO ,  Abhishek SHARMA ,  Van H. LE ,  Cheng-Ying HUANG

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8258

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a first transistor, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor may be a p-type transistor including a channel in a substrate, a first source electrode, and a first drain electrode. A first metal contact may be coupled to the first source electrode, while a second metal contact may be coupled to the first drain electrode. The insulator layer may be next to the first metal contact, and next to the second metal contact. The second transistor may include a second source electrode, and a second drain electrode. The second source electrode may be coupled to the first metal contact, or the second drain electrode may be coupled to the second metal contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20240234422A1

公开(公告)日：2024-07-11

申请号：US18614290

申请日：2024-03-22

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Gilbert DEWEY ,  Anh PHAN ,  Nicole K. THOMAS ,  Urusa ALAAN ,  Seung Hoon SUNG ,  Christopher M. NEUMANN ,  Willy RACHMADY ,  Patrick MORROW ,  Hui Jae YOO ,  Richard E. SCHENKER ,  Marko RADOSAVLJEVIC ,  Jack T. KAVALIEROS ,  Ehren MANNEBACH

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H10B12/00

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/4232 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7853 ,  H10B12/056

Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

公开(公告)号：US20240186398A1

公开(公告)日：2024-06-06

申请号：US18073213

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Anh PHAN ,  Rishabh MEHANDRU ,  Stephen M. CEA ,  Patrick MORROW ,  Jack T. KAVALIEROS ,  Justin WEBER ,  Salim BERRADA

IPC: H01L29/49 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/4991 ,  H01L21/28123 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775

Abstract: Integrated circuit structures having cavity spacers, and methods of fabricating integrated circuit structures having cavity spacers, are described. For example, an integrated circuit structure includes a sub-fin structure over a stack of nanowires. A gate structure is vertically around the stack of nanowires. An internal gate spacer is between vertically adjacent ones of the nanowires and adjacent to the gate structure. A trench contact structure is laterally adjacent to a side of the gate structure. A cavity spacer is laterally between the gate structure and the trench contact structure.

公开(公告)号：US20240145557A1

公开(公告)日：2024-05-02

申请号：US18408346

申请日：2024-01-09

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Aaron LILAK ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY

IPC: H01L29/417

CPC classification number: H01L29/41741 ,  H01L29/41775

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

公开(公告)号：US20240047559A1

公开(公告)日：2024-02-08

申请号：US18381887

申请日：2023-10-19

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Aaron LILAK ,  Patrick MORROW ,  Anh PHAN ,  Cheng-Ying HUANG ,  Ehren MANNEBACH

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.

公开(公告)号：US20230352481A1

公开(公告)日：2023-11-02

申请号：US18219374

申请日：2023-07-07

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Gilbert DEWEY ,  Cheng-Ying HUANG ,  Christopher JEZEWSKI ,  Ehren MANNEBACH ,  Rishabh MEHANDRU ,  Patrick MORROW ,  Anand S. MURTHY ,  Anh PHAN ,  Willy RACHMADY

IPC: H01L27/088 ,  H01L21/768 ,  H01L27/092 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L21/8258 ,  H01L21/84

CPC classification number: H01L27/0886 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/845 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L27/0924 ,  H01L24/94 ,  H01L2224/29188 ,  H01L2224/32145

Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor’s source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor’s channel region and extends downward into a recess that exposes the lower transistor’s source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor’s source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor’s source/drain contact structure.