公开(公告)号：US12106818B2

公开(公告)日：2024-10-01

申请号：US17133484

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Aiswarya M. Pious ,  Raji James ,  Phani K. Alaparthi ,  George Vergis ,  Bill Nale ,  Konika Ganguly

IPC: G11C5/14 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3296 ,  G11C11/4074

CPC classification number: G11C5/148 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3296 ,  G11C5/141 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

Abstract: Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.

公开(公告)号：US11699471B2

公开(公告)日：2023-07-11

申请号：US17030107

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Duane E. Galbi ,  Bill Nale

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/16 ,  G06F13/28 ,  G11C8/18

CPC classification number: G11C7/222 ,  G06F13/1684 ,  G06F13/287 ,  G11C7/1012 ,  G11C8/18

Abstract: An apparatus is described. The apparatus includes logic circuitry to multiplex on a data bus a first data burst, a second data burst, a third data burst and a fourth data burst having different respective base target addresses that respectively target a first memory rank, a second memory rank, a third memory rank and a fourth memory rank. A first data transfer for the first data burst occurs on a first edge of a first pulse of a data strobe signal for the data bus and a second data transfer for the second data burst occurs on a second edge of the first pulse of the data strobe signal. A third data transfer for the third data burst occurs on a first edge of a second pulse of the data strobe signal for the data bus and a fourth data transfer for the fourth data burst occurs on a second edge of the second pulse. The second pulse immediately follows the first pulse on the data strobe signal. The first memory rank, the second memory rank, the third memory rank and the fourth memory rank are on a same memory module.

公开(公告)号：US11688452B2

公开(公告)日：2023-06-27

申请号：US17686287

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Bill Nale ,  Christopher E. Cox

IPC: G11C11/406 ,  G11C11/4096 ,  G06F3/06

CPC classification number: G11C11/40611 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/4096 ,  G11C11/40618

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US11335395B2

公开(公告)日：2022-05-17

申请号：US17062420

申请日：2020-10-02

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Kuljit S. Bains ,  Christopher P. Mozak ,  James A. McCall ,  Akshith Vasanth ,  Bill Nale

IPC: G11C11/4072 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/406

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

公开(公告)号：US11282561B2

公开(公告)日：2022-03-22

申请号：US17157826

申请日：2021-01-25

Applicant: Intel Corporation

Inventor： Bill Nale ,  Christopher E. Cox

IPC: G11C11/406 ,  G11C11/4096 ,  G06F3/06

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US10691626B2

公开(公告)日：2020-06-23

申请号：US16405524

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Bill Nale ,  Raj K. Ramanujan ,  Muthukumar P. Swaminathan ,  Tessil Thomas ,  Taarinya Polepeddi

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0804 ,  G06F9/46 ,  G06F12/0868 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0897 ,  G06F12/0811

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

公开(公告)号：US20200185052A1

公开(公告)日：2020-06-11

申请号：US16795119

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit Bains ,  Wei Chen ,  Rajat Agarwal

IPC: G11C29/00 ,  G11C29/44 ,  G11C11/406 ,  G11C7/10

Abstract: An embodiment of an electronic memory apparatus may include storage media, and logic communicatively coupled to the storage media, the logic to determine if a mode is set to one of a first mode or a second mode, perform a soft post package repair in the first mode, and undo the soft post package repair in the second mode. Other embodiments are disclosed and claimed.

公开(公告)号：US10310547B2

公开(公告)日：2019-06-04

申请号：US15266991

申请日：2016-09-15

Applicant: Intel Corporation

Inventor： George Vergis ,  Kuljit S. Bains ,  Bill Nale

IPC: G06F1/06 ,  G06F13/42 ,  G06F3/06 ,  G06F12/00

Abstract: Techniques to include a mirror of a command/address at a memory device. Techniques to also include interpretation of command/address logic. A memory device located on a dual in-line memory module (DIMM) includes circuitry having logic capable of receiving a command/address signal and mirror a command/address or interpret command/address logic indicated in the command/address signal based on one or more strap pins for the memory device.

公开(公告)号：US20190102325A1

公开(公告)日：2019-04-04

申请号：US15720659

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Mahesh S. Natu ,  Murugasamy K. Nachimuthu ,  Bill Nale

IPC: G06F12/14 ,  G06F12/084

Abstract: Systems, apparatuses and methods may provide for technology that conducts a comparison between an identified capability of a memory device and memory usage rules associated with a processor. The memory usage rules are to identify allowed memory accesses by the processor. The technology further limits access by the processor to the memory device based upon the comparison.

公开(公告)号：US10241943B2

公开(公告)日：2019-03-26

申请号：US15857992

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Bill Nale ,  Raj K. Ramanujan ,  Muthukumar P. Swaminathan ,  Tessil Thomas ,  Taarinya Polepeddi

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/0868 ,  G06F11/10 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0897 ,  G06F9/46 ,  G06F13/40 ,  G06F12/02 ,  G06F12/0811

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol