公开(公告)号：US20180181530A1

公开(公告)日：2018-06-28

申请号：US15392181

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Tomasz Kantecki ,  Ben-Zion Friedman ,  Niall D. McDonnell ,  Bruce Richardson

IPC: G06F13/42 ,  G06F12/0806 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F12/0875 ,  G06F13/126 ,  G06F13/4022 ,  G06F2212/452 ,  G06F2213/0026

Abstract: Examples include techniques for coalescing doorbells in a request message. Example techniques include gathering doorbells to access a device. The gathered are combined in a cache line structure and the cache line structure is written to a cache or buffer for a central processing unit in a single write operation.

公开(公告)号：US20220286399A1

公开(公告)日：2022-09-08

申请号：US17637416

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Niall McDonnell ,  Gage Eads ,  Mrittika Ganguli ,  Chetan Hiremath ,  John Mangan ,  Stephen Palermo ,  Bruce Richardson ,  Edwin Verplanke ,  Praveen Mosur ,  Bradley Chaddick ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L47/125 ,  H04L47/625 ,  H04L47/62 ,  H04L47/6275

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

公开(公告)号：US10884970B2

公开(公告)日：2021-01-05

申请号：US15392181

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Tomasz Kantecki ,  Ben-Zion Friedman ,  Niall D. McDonnell ,  Bruce Richardson

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/12 ,  G06F12/0875

Abstract: Examples include techniques for coalescing doorbells in a request message. Example techniques include gathering doorbells to access a device. The gathered are combined in a cache line structure and the cache line structure is written to a cache or buffer for a central processing unit in a single write operation.

公开(公告)号：US20200042479A1

公开(公告)日：2020-02-06

申请号：US16601137

申请日：2019-10-14

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yipeng Wang ,  Andrew Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs

IPC: G06F13/37 ,  G06F12/0811 ,  G06F13/16 ,  G06F9/54 ,  G06F12/0868

Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

公开(公告)号：US10445272B2

公开(公告)日：2019-10-15

申请号：US16027776

申请日：2018-07-05

Applicant: Intel Corporation

Inventor： Kevin Devey ,  John Browne ,  Chris Macnamara ,  Eoin Walsh ,  Bruce Richardson ,  Andrew Cunningham ,  Niall Power ,  David Hunt ,  Changzheng Wei ,  Eliezer Tamir

IPC: G06F13/38 ,  G06F1/3203 ,  G06F9/455 ,  G06F9/4401

Abstract: A network system includes a central processing unit and a peripheral device in electrical communication with the central processing unit. The peripheral device has at least one power input and a data input. The network system also includes an out of band controller in electrical communication with the central processing unit, the peripheral device, and an external management interface. Responsive to an identified threat, the out of band controller is configured to disable the at least one power input and the data input to the peripheral device, where the disablement indicates to the central processing unit that a hot plug event has occurred with respect to the peripheral device. The out of band controller is also configured to enable auxiliary power to the peripheral device such that the out of band controller remains in communication with the peripheral device during remediation of the identified threat.

公开(公告)号：US10216668B2

公开(公告)日：2019-02-26

申请号：US15087154

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yipeng Wang ,  Jr-Shian Tsai ,  Andrew Herdrich ,  Tsung-Yuan Tai ,  Niall McDonnell ,  Stephen Van Doren ,  David Sonnier ,  Debra Bernstein ,  Hugh Wilkinson ,  Narender Vangati ,  Stephen Miller ,  Gage Eads ,  Andrew Cunningham ,  Jonathan Kenny ,  Bruce Richardson ,  William Burroughs ,  Joseph Hasting ,  An Yan ,  James Clee ,  Te Ma ,  Jerry Pirog ,  Jamison Whitesell

IPC: G06F13/24 ,  G06F13/36 ,  G06F13/40 ,  G06F12/1027

Abstract: Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

公开(公告)号：US20190042506A1

公开(公告)日：2019-02-07

申请号：US16027776

申请日：2018-07-05

Applicant: Intel Corporation

Inventor： Kevin Devey ,  John Browne ,  Chris Macnamara ,  Eoin Walsh ,  Bruce Richardson ,  Andrew Cunningham ,  Niall Power ,  David Hunt ,  Changzheng Wei ,  Eliezer Tamir

IPC: G06F13/38 ,  G06F1/32 ,  G06F9/455

Abstract: A network system includes a central processing unit and a peripheral device in electrical communication with the central processing unit. The peripheral device has at least one power input and a data input. The network system also includes an out of band controller in electrical communication with the central processing unit, the peripheral device, and an external management interface. Responsive to an identified threat, the out of band controller is configured to disable the at least one power input and the data input to the peripheral device, where the disablement indicates to the central processing unit that a hot plug event has occurred with respect to the peripheral device. The out of band controller is also configured to enable auxiliary power to the peripheral device such that the out of band controller remains in communication with the peripheral device during remediation of the identified threat.

公开(公告)号：US20190042419A1

公开(公告)日：2019-02-07

申请号：US16024773

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Bruce Richardson ,  Niall Power ,  Andrew Cunningham ,  David Hunt ,  Kevin Devey ,  Changzheng Wei

IPC: G06F12/084 ,  G06F12/1072

Abstract: Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.

公开(公告)号：US20190042305A1

公开(公告)日：2019-02-07

申请号：US15912746

申请日：2018-03-06

Applicant: Intel Corporation

Inventor： Niall D. McDonnell ,  Debra Bernstein ,  Patrick Fleming ,  Chris Macnamara ,  Andrew Cunningham ,  Bruce Richardson ,  Brendan N. Ryan

IPC: G06F9/48 ,  G06F9/50

Abstract: Technologies for moving workloads between hardware queue managers include a compute device. The compute device includes a set of hardware queue managers. Each hardware queue manager is to manage one or more queues of queue elements and each queue element is indicative of a data set to be operated on by a thread. The compute device also includes circuitry to execute a workload with a first hardware queue manager of the set of hardware queue managers, determine whether a workload migration condition is present, determine whether a second hardware queue manager of the set of hardware queue managers has sufficient capacity to manage a set of queues associated with the workload, move, in response to a determination that the second hardware queue manager does have sufficient capacity, the workload to the second hardware queue manager, and reduce, after the move of the workload to the second hardware queue manager, a power usage of the first hardware queue manager.

公开(公告)号：US09866479B2

公开(公告)日：2018-01-09

申请号：US14750921

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Ren Wang ,  Dong Zhou ,  Bruce Richardson ,  George W. Kennedy ,  Christian Maciocco ,  Sameh Gobriel ,  Tsung-Yuan C. Tai

IPC: H04L12/743 ,  H04L12/851 ,  H04L12/819

CPC classification number: H04L45/7453 ,  H04L47/21 ,  H04L47/2483

Abstract: Technologies for supporting concurrency of a flow lookup table at a network device. The flow lookup table includes a plurality of candidate buckets that each includes one or more entries. The network device includes a flow lookup table write module configured to perform a displacement operation of a key/value pair to move the key/value pair from one bucket to another bucket via an atomic instruction and increment a version counter associated with the buckets affected by the displacement operation. The network device additionally includes a flow lookup table read module to check the version counters during a lookup operation on the flow lookup table to determine whether a displacement operation is affecting the presently read value of the buckets. Other embodiments are described herein and claimed.