公开(公告)号：US10599206B2

公开(公告)日：2020-03-24

申请号：US15939101

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Uksong Kang

IPC: G06F1/00 ,  G06F1/324 ,  G06F3/06 ,  G06F1/3234 ,  G11C7/10 ,  G11C11/4072 ,  G06F1/3296 ,  G11C11/4078 ,  G11C11/4076

Abstract: Examples include techniques to change a mode of operation for a memory device. Examples include using information stored at a memory array of the memory device to program mode registers at the memory device to change the mode of operation to a first mode of operation that corresponds to a frequency set point associated with dynamic voltage and frequency scaling for a processor coupled with the memory device.

公开(公告)号：US10482947B2

公开(公告)日：2019-11-19

申请号：US15911068

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Uksong Kang ,  Nagi Aboulenein

IPC: G06F3/06 ,  G06F11/10 ,  G11C11/408 ,  G11C29/52

Abstract: A multi-die memory device having fixed bandwidth interfaces can selectively connect portions of the interfaces of the multiple memory dies as a memory channel for the multi-die device. The selective application of the interface bits of the memory dies enables the application of ECC (error checking and correction) in memory devices that otherwise have insufficient connectors to exchange ECC information. The device includes circuitry to selectively apply CAS (column address select) signals to the memory dies to selectively connect the connectors of the memory dies. CAS selection can provide various configurations in which selected bits of a first memory die interface are combined with selected bit or bits of a second memory die interface to provide the device interface. The memory dies can operate in byte mode to apply only half of their data I/O (input/output) interface, with CAS doubled up to provide access to the memory arrays.

公开(公告)号：US10146711B2

公开(公告)日：2018-12-04

申请号：US15196014

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit S. Bains ,  George Vergis ,  Christopher E. Cox ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F13/16 ,  G11C14/00 ,  G11C11/4096 ,  G06F13/40

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US11276453B2

公开(公告)日：2022-03-15

申请号：US16879583

申请日：2020-05-20

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Bill Nale

IPC: G11C7/10 ,  G11C11/406 ,  G06F3/06 ,  G11C11/4093 ,  G11C29/02

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

公开(公告)号：US10950288B2

公开(公告)日：2021-03-16

申请号：US16370578

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Bill Nale ,  Christopher E. Cox

IPC: G11C11/406 ,  G11C11/4096 ,  G06F3/06

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US10755753B2

公开(公告)日：2020-08-25

申请号：US16277797

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Uksong Kang ,  Christopher E. Cox

IPC: G11C7/10 ,  G11C11/406 ,  G11C11/408 ,  G11C7/22 ,  H04L29/06 ,  G11C16/10 ,  G11C11/4093 ,  G11C11/4096 ,  G06K9/00

Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.

公开(公告)号：US10430335B2

公开(公告)日：2019-10-01

申请号：US15388752

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Saher Abu Rahme ,  Christopher E. Cox ,  Joydeep Ray

IPC: G06F12/08 ,  G06F12/0804 ,  G06F1/3225 ,  G06F3/06 ,  G06F12/0897 ,  G06F12/0868

Abstract: A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.

公开(公告)号：US09871519B2

公开(公告)日：2018-01-16

申请号：US15359573

申请日：2016-11-22

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Nadav Bonen ,  Christopher E. Cox ,  Alexey Kostinsky

IPC: H03K19/00 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/0185 ,  G06F13/40 ,  G06F3/06

CPC classification number: H03K19/0005 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/4086 ,  H03K19/0008 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

公开(公告)号：US20170255387A1

公开(公告)日：2017-09-07

申请号：US15277159

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Kuljit S. Bains ,  James A. McCall

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/16 ,  G11C7/10 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/2263 ,  G11C2207/229

Abstract: Examples include techniques to cause a content pattern to be stored to memory cells of a memory device. Example techniques include forwarding a content pattern to a memory device for storage to registers maintained at the memory device. A command is generated and forwarded to the memory device to cause the content pattern to be stored to at least a portion of memory cells for the memory device responsive to a write request to the memory device having a matching content pattern.

公开(公告)号：US11688452B2

公开(公告)日：2023-06-27

申请号：US17686287

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Bill Nale ,  Christopher E. Cox

IPC: G11C11/406 ,  G11C11/4096 ,  G06F3/06

CPC classification number: G11C11/40611 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/4096 ,  G11C11/40618

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.