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公开(公告)号：US20160179647A1
公开(公告)日：2016-06-23
申请号：US14581000
申请日：2014-12-23
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Daniel S. Froelich
IPC: G06F11/263 , G06F11/22
CPC classification number: G06F11/263 , G06F11/221 , G06F13/00 , G06F13/4022 , G06F13/4027 , G06F13/42 , G06F13/4282 , H03M13/09 , H04L1/0083 , Y02D10/14 , Y02D10/151
Abstract: An apparatus that includes a serial interconnect is provided, wherein the serial interconnect includes test logic to send a number of reporting messages, wherein each reporting message is associated with a link sub-segment in a link in the serial interconnect, and each reporting message comprises a status region for the associated link sub-segment to report transmission errors. The test logic also includes analysis logic to record errors in the link sub-segment.
Abstract translation: 提供一种包括串行互连的装置，其中串行互连包括发送多个报告消息的测试逻辑，其中每个报告消息与串行互连中的链路中的链路子段相关联，并且每个报告消息包括 用于相关联的链路子段的状态区域来报告传输错误。 测试逻辑还包括分析逻辑，以记录链接子段中的错误。
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公开(公告)号：US11630480B2
公开(公告)日：2023-04-18
申请号：US15920249
申请日：2018-03-13
Applicant: Intel Corporation
Inventor： David J. Harriman , Debendra Das Sharma , Daniel S. Froelich , Sean O. Stalley
IPC: G06F1/14 , G06F13/42 , H04B1/7073 , H04L69/14
Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.
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公开(公告)号：US11157350B2
公开(公告)日：2021-10-26
申请号：US15929946
申请日：2020-05-29
Applicant: Intel Corporation
Inventor： Daniel S. Froelich , Debendra Das Sharma , Fulvio Spagna , Per E. Fornberg , David Edward Bradley
Abstract: There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.
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公开(公告)号：US20210089421A1
公开(公告)日：2021-03-25
申请号：US17114089
申请日：2020-12-07
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Daniel S. Froelich
Abstract: A retimer device is provided that includes an elasticity buffer, a receiver, and a controller. The elasticity buffer adds or subtracts data in the elasticity buffer to compensate for different bit rates of two devices to be connected over a link, where the retimer is positioned between the two devices on the link. The receiver receives a data stream to be sent between the two devices on the link. The controller determines, from the data stream, a modification to one or more characteristics of the link, and causes size of the elasticity buffer to be changed from a first size to a second size based on the modification.
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公开(公告)号：US10853212B2
公开(公告)日：2020-12-01
申请号：US15990372
申请日：2018-05-25
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Daniel S. Froelich
Abstract: A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.
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Patent Agency Ranking
公开(公告)号：US20180285227A1
公开(公告)日：2018-10-04
申请号：US15476571
申请日：2017-03-31
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Daniel S. Froelich
IPC: G06F11/30 , H04L1/20 , H04L29/06 , H04L29/08 , H04L12/933
Abstract: A retimer device is provided that includes an elasticity buffer, a receiver, and a controller. The elasticity buffer adds or subtracts data in the elasticity buffer to compensate for different bit rates of two devices to be connected over a link, where the retimer is positioned between the two devices on the link. The receiver receives a data stream to be sent between the two devices on the link. The controller determines, from the data stream, a modification to one or more characteristics of the link, and causes size of the elasticity buffer to be changed from a first size to a second size based on the modification.
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公开(公告)号：US20170351640A1
公开(公告)日：2017-12-07
申请号：US15612209
申请日：2017-06-02
Applicant: Intel Corporation
Inventor： Manisha Nilange , Steven K. Krooswyk , Ernesto Rosales Galvan , Antonio Orozco Ramirez , Daniel S. Froelich , Mohiuddin M. Mazumder
CPC classification number: G06F15/7814 , G06F13/4068 , G06F13/4291 , G06F2213/0026
Abstract: A retimer device is presented with a retimer with an array of connectors on a surface of the device that are configured to form a ball grid array to electrically connect the chip package to a circuit board. At least a portion of the connectors in the array are arranged on the surface in a hexagonal pattern. The connectors are assigned to the plurality of high speed connectors to arrange each high speed differential pair in the plurality of high speed differential pairs substantially orthogonally with respect to one or more other differential pairs in the plurality of high speed differential pairs.
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公开(公告)号：US09779053B2
公开(公告)日：2017-10-03
申请号：US14580918
申请日：2014-12-23
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Daniel S. Froelich , Venkatraman Iyer , Michelle C. Jen , Rahul R. Shah , Eric M. Lee
CPC classification number: G06F13/4068 , G06F13/1642 , G06F13/1673 , G06F13/385 , G06F13/4282
Abstract: An apparatus that includes a physical interface for a serial interconnect is provided. The physical interface includes a buffer that is selectable to function as a drift buffer or an elastic buffer by a voltage level on a buffer control line. The physical interface also includes encoding logic that can be enabled or disabled by a voltage level on a logic control line. Further, the physical interface also includes and an ordered set generator that can be enabled or disabled by a voltage level on a communications control line.
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19.发明授权Method, apparatus and system for measuring latency in a physical unit of a circuit 有权用于测量电路物理单元中的延迟的方法，装置和系统公开(公告)号：US09558145B2
公开(公告)日：2017-01-31
申请号：US14991293
申请日：2016-01-08
Applicant: Intel Corporation
Inventor： David J. Harriman , Mahesh Wagh , Abdul R. Ismail , Daniel S. Froelich
CPC classification number: G06F13/4282 , G06F1/14 , G06F13/00 , G06F13/385 , H04L43/0858 , H04L43/106
Abstract: In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，装置包括根据本地时钟信号在起始值和结束值之间进行计数的计数器，用于存储计数器的输出的第一寄存器，用于存储接收到的计数器输出的样本的镜像弹性缓冲器 第一寄存器，其中反射镜弹性缓冲器用于映射接收器电路的弹性缓冲器，以及分辨率逻辑，用于从反射镜弹性缓冲器接收计数器输出样本，以及从计数器输出的当前计数器值，并确定传送 数据元素至少部分地基于计数器输出采样和当前计数器值来遍历接收器电路的等待时间。 描述和要求保护其他实施例。
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公开(公告)号：US09552269B2
公开(公告)日：2017-01-24
申请号：US14581000
申请日：2014-12-23
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Daniel S. Froelich
CPC classification number: G06F11/263 , G06F11/221 , G06F13/00 , G06F13/4022 , G06F13/4027 , G06F13/42 , G06F13/4282 , H03M13/09 , H04L1/0083 , Y02D10/14 , Y02D10/151
Abstract: An apparatus that includes a serial interconnect is provided, wherein the serial interconnect includes test logic to send a number of reporting messages, wherein each reporting message is associated with a link sub-segment in a link in the serial interconnect, and each reporting message comprises a status region for the associated link sub-segment to report transmission errors. The test logic also includes analysis logic to record errors in the link sub-segment.
Abstract translation: 提供一种包括串行互连的装置，其中串行互连包括发送多个报告消息的测试逻辑，其中每个报告消息与串行互连中的链路中的链路子段相关联，并且每个报告消息包括 用于相关联的链路子段的状态区域来报告传输错误。 测试逻辑还包括分析逻辑，以记录链接子段中的错误。
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