公开(公告)号：US20230418655A1

公开(公告)日：2023-12-28

申请号：US18207870

申请日：2023-06-09

Applicant: Intel Corporation

Inventor： Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Narayan RANGANATHAN ,  Stephen R. VAN DOREN ,  Joseph NUZMAN ,  Niall D. MCDONNELL ,  Michael A. O'HANLON ,  Lokpraveen B. MOSUR ,  Tracy Garrett DRYSDALE ,  Eriko NURVITADHI ,  Asit K. MISHRA ,  Ganesh VENKATESH ,  Deborah T. MARR ,  Nicholas P. CARTER ,  Jonathan D. PEARCE ,  Edward T. GROCHOWSKI ,  Richard J. GRECO ,  Robert VALENTINE ,  Jesus CORBAL ,  Thomas D. FLETCHER ,  Dennis R. BRADFORD ,  Dwight P. MANLEY ,  Mark J. CHARNEY ,  Jeffrey J. COOK ,  Paul CAPRIOLI ,  Koichi YAMADA ,  Kent D. GLOSSOP ,  David B. SHEFFIELD

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/48 ,  G06F9/3001 ,  G06F9/383 ,  G06F9/3004 ,  G06F9/30036

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US20220164218A1

公开(公告)日：2022-05-26

申请号：US17381521

申请日：2021-07-21

Applicant: Intel Corporation

Inventor： Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Narayan RANGANATHAN ,  Stephen R. VAN DOREN ,  Joseph NUZMAN ,  Niall D. MCDONNELL ,  Michael A. O'HANLON ,  Lokpraveen B. MOSUR ,  Tracy Garrett DRYSDALE ,  Eriko NURVITADHI ,  Asit K. MISHRA ,  Ganesh VENKATESH ,  Deborah T. MARR ,  Nicholas P. CARTER ,  Jonathan D. PEARCE ,  Edward T. GROCHOWSKI ,  Richard J. GRECO ,  Robert VALENTINE ,  Jesus CORBAL ,  Thomas D. FLETCHER ,  Dennis R. BRADFORD ,  Dwight P. MANLEY ,  Mark J. CHARNEY ,  Jeffrey J. COOK ,  Paul CAPRIOLI ,  Koichi YAMADA ,  Kent D. GLOSSOP ,  David B. SHEFFIELD

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US20210373934A1

公开(公告)日：2021-12-02

申请号：US17404897

申请日：2021-08-17

Applicant: Intel Corporation

Inventor： Sanjay KUMAR ,  Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Philip R. LANTZ ,  Jason W. BRANDT ,  Vedvyas SHANBHOGUE ,  Utkarsh Y. KAKAIYA ,  Kun TIAN

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1045 ,  G06F12/109

Abstract: Implementations of the disclosure provide a processing device comprising an address translation circuit to intercept a work request from an I/O device. The work request comprises a first ASID to map to a work queue. A second ASID of a host is allocated for the first ASID based on the work queue. The second ASID is allocated to at least one of: an ASID register for a dedicated work queue (DWQ) or an ASID translation table for a shared work queue (SWQ). Responsive to receiving a work submission from the SVM client to the I/O device, the first ASID of the application container is translated to the second ASID of the host machine for submission to the I/O device using at least one of: the ASID register for the DWQ or the ASID translation table for the SWQ based on the work queue associated with the I/O device.

公开(公告)号：US20210117535A1

公开(公告)日：2021-04-22

申请号：US17114246

申请日：2020-12-07

Applicant: INTEL CORPORATION

Inventor： Michael LEMAY ,  David M. DURHAM ,  Michael E. KOUNAVIS ,  Barry E. HUNTLEY ,  Vedvyas SHANBHOGUE ,  Jason W. BRANDT ,  Josh TRIPLETT ,  Gilbert NEIGER ,  Karanvir GREWAL ,  Baiju PATEL ,  Ye ZHUANG ,  Jr-Shian TSAI ,  Vadim SUKHOMLINOV ,  Ravi SAHITA ,  Mingwei ZHANG ,  James C. FARWELL ,  Amitabh DAS ,  Krishna BHUYAN

IPC: G06F21/53 ,  G06F12/02

Abstract: Disclosed embodiments relate to encoded inline capabilities. In one example, a system includes a trusted execution environment (TEE) to partition an address space within a memory into a plurality of compartments each associated with code to execute a function, the TEE further to assign a message object in a heap to each compartment, receive a request from a first compartment to send a message block to a specified destination compartment, respond to the request by authenticating the request, generating a corresponding encoded capability, conveying the encoded capability to the destination compartment, and scheduling the destination compartment to respond to the request, and subsequently, respond to a check capability request from the destination compartment by checking the encoded capability and, when the check passes, providing a memory address to access the message block, and, otherwise, generating a fault, wherein each compartment is isolated from other compartments.

公开(公告)号：US20210051149A1

公开(公告)日：2021-02-18

申请号：US17084406

申请日：2020-10-29

Applicant: Intel Corporation

Inventor： Barry E. HUNTLEY ,  Gilbert NEIGER ,  H. Peter ANVIN ,  Asit K. MALLICK ,  Adriaan VAN DE VEN ,  Scott D. RODGERS

IPC: H04L29/06 ,  G06F21/74

Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.

公开(公告)号：US20240248722A1

公开(公告)日：2024-07-25

申请号：US18626629

申请日：2024-04-04

Applicant: Intel Corporation

Inventor： Eliezer WEISSMANN ,  Mark CHARNEY ,  Michael MISHAELI ,  Robert VALENTINE ,  Itai RAVID ,  Jason W. BRANDT ,  Gilbert NEIGER ,  Baruch CHAIKIN ,  Efraim ROTEM

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/3836 ,  G06F9/3842

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US20240220248A1

公开(公告)日：2024-07-04

申请号：US18091318

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Vivekananthan SANJEEPAN ,  Gilbert NEIGER ,  Michael ESPIG

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30181

Abstract: Techniques to restrict vector length in a processor are described. A method of an aspect that may be performed by a processor includes executing first instances of vector instructions having respective opcode values regardless of whether they specify wider vectors of a wider vector width or narrower vectors of a narrower vector width, when a control value is a first value. The method also includes executing second instances of vector instructions having the respective opcode values when they specify narrower vectors of the narrower vector width, but do not specify wider vectors of the wider vector width, when the control value is a second different value. The method also includes preventing execution of third instances of vector instructions having the respective opcode values when they specify wider vectors of the wider vector width, when the control value is the second value. Other methods, processors, and systems are disclosed.

公开(公告)号：US20220155847A1

公开(公告)日：2022-05-19

申请号：US17559170

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Konstantin ANANYEV ,  Anatoly BURAKOV ,  David HUNT ,  Chris MACNAMARA ,  Edwin VERPLANKE ,  Omkar MASLEKAR ,  Gilbert NEIGER ,  Rajesh M. SANKARAN

IPC: G06F1/3296 ,  G06F3/06

Abstract: Examples described herein relate to circuitry to cause a processor to enter reduced power consumption state and circuitry to, based on a write to one or more of multiple memory regions, cause the processor to exit reduced power consumption state, wherein the multiple memory regions store receive descriptors associated with one or more packets received by a network interface device. In some examples, multiple memory regions are defined by a driver of the network interface device. In some examples, the reduced power consumption state comprises a TPAUSE state.

公开(公告)号：US20210303304A1

公开(公告)日：2021-09-30

申请号：US16833599

申请日：2020-03-28

Applicant: Intel Corporation

Inventor： Vedvyas SHANBHOQUE ,  Gilbert NEIGER ,  Deepak K. GUPTA ,  H. Peter ANVIN

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/54 ,  G06F16/176

Abstract: An apparatus and method for efficiently managing shadow stacks. For example, one embodiment of a processor comprises: a plurality of registers to store a plurality of shadow stack pointers (SSPs), each SSP associated with a different event priority; event processing circuitry to select a first SSP of the plurality of SSPs from a first register of the plurality of registers responsive to receipt of a first event associated with a first event priority level, the first SSP usable to identify a top of a first shadow stack; verification and utilization checking circuitry to determine whether the first SSP has been previously verified, wherein if the first SSP has not been previously verified then initiating a set of atomic operations to verify the first SSP and confirm that the first SSP is not in use, the set of atomic operations using a locking operation to lock data until the set of atomic operations are complete, and wherein if the first SSP has been previously verified, then re-verifying the first SSP and confirming that the first SSP is not in use without using the locking operation.

公开(公告)号：US20210258311A1

公开(公告)日：2021-08-19

申请号：US17307992

申请日：2021-05-04

Applicant: Intel Corporation

Inventor： Barry E. HUNTLEY ,  Gilbert NEIGER ,  H. Peter ANVIN ,  Asit K. MALLICK ,  Adriaan VAN DE VEN ,  Scott D. RODGERS

IPC: H04L29/06 ,  G06F21/74

Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.