公开(公告)号：US09406615B2

公开(公告)日：2016-08-02

申请号：US14139970

申请日：2013-12-24

Applicant: INTEL CORPORATION

Inventor： Christopher J. Jezewski ,  David J. Michalak ,  Kanwal Jit Singh ,  Alan M. Myers

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5329 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76838 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (κ-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer. Some embodiments can be utilized, for example, in processes involving atomic layer deposition (ALD)-based and/or chemical vapor deposition (CVD)-based backend metallization of highly porous, ultra-low-κ (ULK) dielectric materials.

Abstract translation: 公开了用于在多孔电介质材料中形成互连的技术。 根据一些实施例，可以通过用诸如氮化钛（TiN），二氧化钛（TiO 2）或其它合适的牺牲材料的牺牲孔填充材料填充其孔来临时减小主介质层的孔隙率， 与互连的金属化和介电材料相比，具有高蚀刻选择性。 在填充电介质层内形成互连之后，可以从主电介质的孔中去除牺牲孔填充材料。 在某些情况下，可以对主介电层的介电常数（κ值），泄漏性能和/或时间依赖的介电击穿（TDDB）性能产生最小或其他可忽略的影响来进行去除和固化。 一些实施例可以用于例如涉及基于原子层沉积（ALD）的和/或化学气相沉积（CVD）的高多孔，超低κ（ULK）电介质材料的后端金属化的工艺。

公开(公告)号：US09379010B2

公开(公告)日：2016-06-28

申请号：US14163323

申请日：2014-01-24

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Jasmeet S. Chawla ,  Kanwal Jit Singh ,  Alan M. Myers ,  Elliot N. Tan ,  Richard E. Schenker

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7688 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to form interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminate the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allow for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.

Abstract translation: 用于在电介质层内形成具有窄间距互连结构的互连层的工艺，其中用于形成互连结构的沟槽和通孔在金属化之前具有相对低的纵横比。 当沉积时，低纵横比可以减少或基本上消除在金属化材料内形成的空隙的潜力。 本文的实施例可以通过允许在金属化之前去除用于形成沟槽和通孔的结构的工艺来实现这种相对低的纵横比。

公开(公告)号：US10593627B2

公开(公告)日：2020-03-17

申请号：US15574816

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Kanwal Jit Singh ,  Kevin Lin ,  Robert Lindsey Bristol

IPC: H01L23/532 ,  H01L29/06 ,  H01L23/522 ,  H01L21/768 ,  H01L23/498 ,  H01L21/764

Abstract: Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a plurality of openings are formed in a first sacrificial material layer. Conductive vias and dielectric pillars may be formed in the openings. A second sacrificial material layer may then be formed over the pillars, the vias, and the first sacrificial material layer. In an embodiment, a permeable etchstop layer is formed over a top surface of the second sacrificial layer. Embodiments then include forming an interconnect line in the second sacrificial material layer. In an embodiment, the first and second sacrificial material layers are removed through the permeable etchstop layer after the interconnect line has been formed. According to an embodiment, the permeable etchstop layer may then be stuffed with a fill material in order to harden the permeable etchstop layer.

公开(公告)号：US10147639B2

公开(公告)日：2018-12-04

申请号：US15523330

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Kanwal Jit Singh ,  Alan M. Myers

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/768 ,  H01L29/78 ,  H01L21/84 ,  H01L21/764 ,  H01L23/522 ,  H01L23/532

Abstract: A method including forming a sacrificial material between metal lines of an integrated circuit structure; forming a mask on the sacrificial material; and after forming the mask, removing the sacrificial material to leave a void between the metal lines. An apparatus including an integrated circuit substrate; a first metallization level on the substrate; a second metallization; and a mask disposed between the first metallization level and the second metallization level, the mask including a dielectric material having a porosity select to allow mass transport therethrough, wherein each of the first metallization level and the second metallization level comprises a plurality of metal lines and a portion of adjacent metal lines of at least one of the first metallization level and the second metallization level are separated by voids.

公开(公告)号：US10032643B2

公开(公告)日：2018-07-24

申请号：US15528736

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Jasmeet S. Chawla ,  Ruth A. Brain ,  Richard E. Schenker ,  Kanwal Jit Singh ,  Alan M. Myers

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/48 ,  H01L23/522

Abstract: Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.

公开(公告)号：US20170207120A1

公开(公告)日：2017-07-20

申请号：US15477506

申请日：2017-04-03

Applicant: INTEL CORPORATION

Inventor： Boyan Boyanov ,  Kanwal Jit Singh

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel The channel is configured to contain the capping layer within the width of the conductive line.

公开(公告)号：US09455224B2

公开(公告)日：2016-09-27

申请号：US14746315

申请日：2015-06-22

Applicant: INTEL CORPORATION

Inventor： Boyan Boyanov ,  Kanwal Jit Singh ,  James Clarke ,  Alan Myers

IPC: H01L21/76 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

Abstract translation: 公开了能够改善未上行的导电互连特征与相邻导电特征之间的短路裕度的技术。 在一些实施例中，可以将蚀刻施加到其中具有一个或多个导电特征的绝缘体层，使得绝缘体层凹入导电特征的顶部下方，并且导电特征的边缘被倒圆或以其它方式软化。 然后可以在导电特征和绝缘体材料上沉积保形蚀刻层。 可以在保形蚀刻阻挡层上方沉积第二绝缘体层，并且互连特征可以穿过第二绝缘体层和保形蚀刻阻挡层以与导电特征之一的圆形部分连接。 在一些实施例中，互连特征是未上通孔，并且通孔的未上覆部分可以穿透或不穿透保形阻挡层。

公开(公告)号：US20150294935A1

公开(公告)日：2015-10-15

申请号：US14746315

申请日：2015-06-22

Applicant: INTEL CORPORATION

Inventor： Boyan Boyanov ,  Kanwal Jit Singh ,  James Clarke ,  Alan Myers

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

Abstract translation: 公开了能够改善未上行的导电互连特征与相邻导电特征之间的短路裕度的技术。 在一些实施例中，可以将蚀刻施加到其中具有一个或多个导电特征的绝缘体层，使得绝缘体层凹入导电特征的顶部下方，并且导电特征的边缘被倒圆或以其它方式软化。 然后可以在导电特征和绝缘体材料上沉积保形蚀刻层。 可以在保形蚀刻阻挡层上方沉积第二绝缘体层，并且互连特征可以穿过第二绝缘体层和保形蚀刻阻挡层以与导电特征之一的圆形部分连接。 在一些实施例中，互连特征是未上通孔，并且通孔的未上覆部分可以穿透或不穿透保形阻挡层。