公开(公告)号：US11309900B2

公开(公告)日：2022-04-19

申请号：US16913933

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kuan-Yueh Shen ,  Nasser A. Kurd ,  John Fallin

IPC: H03L7/099 ,  H03L7/089 ,  H01R13/66 ,  H03L7/189

Abstract: Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.

公开(公告)号：US20210082481A1

公开(公告)日：2021-03-18

申请号：US17107704

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： Navindra Navaratnam ,  Nasser A. Kurd ,  Bee Min Teng ,  Raymond Chong ,  Nasirul I. Chowdhury ,  Ali M. El-Husseini

IPC: G11C7/22 ,  H03K5/135 ,  G11C7/10 ,  H01L25/18

Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.

公开(公告)号：US20210055921A1

公开(公告)日：2021-02-25

申请号：US16550134

申请日：2019-08-23

Applicant: Intel Corporation

Inventor： Julien Sebot ,  Edward A. Burton ,  Nasser A. Kurd ,  Jonathan Douglas

IPC: G06F8/41 ,  G06F9/30 ,  H03L7/08

Abstract: An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.

公开(公告)号：US20200327914A1

公开(公告)日：2020-10-15

申请号：US16914310

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Navindra Navaratnam ,  Nasser A. Kurd ,  Bee Min Teng ,  Raymond Chong ,  Nasirul I. Chowdhury ,  Ali M. El-Husseini

IPC: G11C7/22 ,  H03K5/135 ,  G11C7/10 ,  H01L25/18

Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.

公开(公告)号：US10790838B1

公开(公告)日：2020-09-29

申请号：US16412165

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Praveen Mosalikanti ,  Vaughn J. Grossnickle ,  Syed Feruz Syed Farooq ,  Mark Neidengard ,  Nasser A. Kurd

IPC: H03L7/189 ,  H03L7/099 ,  H03L7/197 ,  H03L7/085

Abstract: Dynamic voltage frequency scaling to transition to a target clock frequency and associated target voltage is provided. Dynamic voltage frequency scaling to a different clock frequency is performed by gradually changing the clock frequency using discrete variable-size steps, while dynamically switching to faster or slower reference clock frequencies as appropriate to harmonize the frequency trajectory with system requirements.

公开(公告)号：US11211934B2

公开(公告)日：2021-12-28

申请号：US17028923

申请日：2020-09-22

Applicant: Intel Corporation

Inventor： Praveen Mosalikanti ,  Qi Wang ,  Mark L. Neidengard ,  Vaughn J. Grossnickle ,  Nasser A. Kurd

IPC: H03K3/03 ,  H03L1/00 ,  H03L7/08 ,  H03L7/099

Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

公开(公告)号：US11048284B2

公开(公告)日：2021-06-29

申请号：US16566368

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Praveen Mosalikanti ,  Gerhard Schrom ,  Vaughn J. Grossnickle ,  Nasser A. Kurd

IPC: G05F1/625 ,  G01R19/165 ,  H03K5/24 ,  H03L7/093 ,  H03L7/06

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.

公开(公告)号：US10928886B2

公开(公告)日：2021-02-23

申请号：US16285051

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Praveen Mosalikanti ,  Nasser A. Kurd ,  Alexander Gendler

IPC: G06F1/3296 ,  H03L7/093 ,  G01R19/25 ,  H03L7/095 ,  H03K5/24 ,  H03K19/20

Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.

公开(公告)号：US10707877B1

公开(公告)日：2020-07-07

申请号：US16455162

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Turbo Majumder ,  Minki Cho ,  Carlos Tokunaga ,  Praveen Mosalikanti ,  Nasser A. Kurd ,  Muhammad M. Khellah

IPC: G06F1/08 ,  H03L5/00 ,  H03L7/099

Abstract: Switched adaptive clocking is provided. A switched adaptive clocking circuit includes a digitally controlled oscillator, a clock generator and a glitch-free multiplexer. The switched adaptive clocking circuit to adaptively switch a source of an output clock from a main clock generated by a clock source to a digitally controlled oscillator clock generated by a digitally controlled oscillator upon detection of a voltage droop, and to quickly switch back to the main clock after recovery from the voltage droop.

公开(公告)号：US10686582B1

公开(公告)日：2020-06-16

申请号：US16285056

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Gerald Pasdast ,  Nasser A. Kurd ,  Peipei Wang ,  Yingyu Miao ,  Lakshmipriya Seshan ,  Ishaan S. Shah

IPC: H04L7/00 ,  H03L7/081 ,  H03L7/093 ,  H03K5/00 ,  G06F1/08 ,  G06F1/10 ,  G06F1/06 ,  H03K3/037

Abstract: An apparatus and method is provided that compensates for the supply droops to minimize strobe shifts and to regain eye margin. The apparatus includes a droop detector to detect voltage droops at one or more trip (or threshold) levels and these detected voltage droops are translated to a shift in clock phase setting. For example, propagation delay of a delay locked loop (DLL) and/or clock edge selection from a phase interpolator (PI) is adjusted according to the detected voltage droop levels to maintain a trained relationship between the sampling clock strobe and data eye. A lookup table is used to determine a PI code or a DLL propagation delay code corresponding to a voltage droop level.