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公开(公告)号：US09946598B1
公开(公告)日：2018-04-17
申请号：US15282640
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Ravi H. Motwani
CPC classification number: G06F11/1068 , G11C29/52 , H03M13/005
Abstract: Systems, apparatuses and methods may provide for recording, if a non-volatile memory (NVM) location satisfies an open circuit condition, open circuit location information associated with the NVM location. Additionally, a shift of one or more bits may be conducting during a write of a codeword to the NVM location to avoid open circuit in the NVM location. Moreover, an end of a parity portion of the codeword may be punctured by an amount of the shift. In one example, the end of the parity portion includes a last circulant of the codeword.
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公开(公告)号：US09912355B2
公开(公告)日：2018-03-06
申请号：US14866506
申请日：2015-09-25
Applicant: INTEL CORPORATION
Inventor： Ravi H. Motwani
CPC classification number: H03M13/29 , G06F11/1012 , G06F11/1068 , G11C29/52 , G11C2029/0411 , H03M13/2906
Abstract: In one embodiment, a distributed concatenated error correction logic is disposed on separate integrated circuit dies to facilitate efficiency. In one embodiment, an inner error correction code logic of the distributed concatenated error correction logic is disposed on an integrated circuit die of a memory circuit and an outer error correction code logic of the distributed concatenated error correction logic is disposed on an integrated circuit die of a memory controller. In one aspect, it is believed that such an arrangement may be employed to increase the usefulness of memory controllers for later generation memory circuits. Other aspects are described herein.
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公开(公告)号：US20180006667A1
公开(公告)日：2018-01-04
申请号：US15197953
申请日：2016-06-30
Applicant: Intel Corporation
Inventor： Ravi H. Motwani
CPC classification number: H03M13/2909 , G06F11/1076 , H03M13/09 , H03M13/152 , H03M13/2939 , H03M13/616 , H04L1/00 , H04L1/0054 , H04L1/0057 , H04L69/324
Abstract: Technologies for providing efficient error correction with half product codes include an apparatus having a memory to store data and a controller to manage read and write operations of the memory. The controller is to obtain, in response to a write request, data to write to the memory. The controller is further to encode the data with a half product code to define a matrix that includes at least one matrix element based on a soft decision error correction encoder algorithm and at least one other matrix element based on a hard decision error correction encoder algorithm. Additionally, the controller is to write the half product code to the memory.
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公开(公告)号：US09798622B2
公开(公告)日：2017-10-24
申请号：US14557070
申请日：2014-12-01
Applicant: INTEL CORPORATION
Inventor： Ravi H. Motwani
CPC classification number: G06F11/1092 , G06F11/1012 , G06F11/1068 , G06F11/1076 , G06F11/108 , G06F12/0246 , H03M13/152 , H03M13/2909
Abstract: Described is an apparatus which comprises: a first encoder to encode data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion, and each codeword of the set to be stored in a separate memory bank of a memory block; and a second encoder to encode the data portions of each codeword of the set with a second error correction scheme, the second encoder to generate a combined codeword having a data portion and a corresponding parity portion, wherein the corresponding parity portion of the combined codeword is to be stored in an additional memory bank of the memory block.
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15.发明授权Using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units 有权使用来自多个存储单元和奇偶校验存储单元的可靠性信息来恢复存储单元中的一个存储单元的数据公开(公告)号：US09588841B2
公开(公告)日：2017-03-07
申请号：US14499078
申请日：2014-09-26
Applicant: INTEL CORPORATION
Inventor： Andre Lei , Scott Nelson , Zion S. Kwok , Ravi H. Motwani
CPC classification number: G06F11/1068 , G06F11/1012 , G11C5/143 , G11C29/52 , H03M13/1105
Abstract: Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.
Abstract translation: 提供了使用来自多个存储单元的可靠性信息和奇偶校验存储单元来恢复存储单元中的一个故障存储单元的数据的方法，系统和装置。 在包括目标数据存储单元和奇偶校验存储单元以外的数据存储单元的每个存储单元中执行码字的解码操作，以产生可靠性信息。 响应于对于至少一个附加的故障存储单元的解码操作失败，所述至少一个附加故障存储单元包括除了解码失败的目标数据存储单元之外的数据和/或奇偶校验存储单元，对于至少一个附加的数据部分的数据部分获得可靠性信息 存储单元故障 从目标数据存储单元以外的存储单元获得的可靠性信息用于生成目标数据存储单元中的数据单元的校正数据。
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Patent Agency Ranking
16.发明申请APPARATUS AND METHOD FOR DETECTING AND MITIGATING BIT-LINE OPENS IN FLASH MEMORY 有权用于检测和减轻闪存中的位线打开的装置和方法公开(公告)号：US20160283320A1
公开(公告)日：2016-09-29
申请号：US14671140
申请日：2015-03-27
Applicant: Intel Corporation
Inventor： Ravi H. Motwani , Pranav Kalavade
CPC classification number: H03M13/1515 , G06F11/1012 , G06F11/1024 , G06F11/1068 , G11C7/1006 , G11C16/0483 , G11C29/025 , G11C29/42 , G11C29/52 , G11C2029/1204 , H03M13/1102
Abstract: Described is a method which comprises performing a first read from a portion of a non-volatile memory, the first read to provide a first codeword; decoding the first codeword; determining whether the decoding operation failed; performing a second read from the portion of the non-volatile memory when it is determined that the decoding operation failed, the second read to provide a second codeword; and decoding the second codeword with an errors-and-erasures decoding process.
Abstract translation: 描述了一种方法，其包括从非易失性存储器的一部分执行第一读取，第一读取以提供第一代码字; 解码第一码字; 确定解码操作是否失败; 当确定解码操作失败时，从非易失性存储器的一部分执行第二次读取，第二次读取以提供第二代码字; 以及用错误和擦除解码过程对第二码字进行解码。
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公开(公告)号：US20160085621A1
公开(公告)日：2016-03-24
申请号：US14493956
申请日：2014-09-23
Applicant: Intel Corporation
Inventor： Ravi H. Motwani , Kiran Pangal
CPC classification number: G06F11/1008 , G06F11/10 , G06F11/1068 , G06F11/108 , G06F12/0246 , G11C29/52 , G11C2029/0411 , H03M13/1108
Abstract: Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device to read a line of data to the memory device, wherein the data is spread across a plurality (N) of dies and comprises an error correction code (ECC) spread across the plurality (N) of dies, retrieve the line of data from the memory device, perform an error correction code (ECC) check on the line of data retrieved from the memory device, and invoke a recovery algorithm in response to an error in the ECC check on the line of data retrieved from the memory device. Other embodiments are also disclosed and claimed.
Abstract translation: 描述了存储器中恢复算法的装置，系统和方法。 在一个实施例中，控制器包括用于接收来自主机设备的读请求以读取到存储器设备的数据线的逻辑，其中数据分布在多个（N）个管芯上，并且包括纠错码（ECC） 分布在多个（N）个管芯上，从存储器件检索数据线，对从存储器件检索的数据行执行纠错码（ECC）校验，并响应错误调用恢复算法 在ECC中检查从存储器件检索的数据行。 还公开并要求保护其他实施例。
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18.发明申请MULTI-LEVEL CELL (MLC) NON-VOLATILE MEMORY DATA READING METHOD AND APPARATUS 审中-公开多级电池（MLC）非易失性存储器数据读取方法和装置公开(公告)号：US20160012887A1
公开(公告)日：2016-01-14
申请号：US14749337
申请日：2015-06-24
Applicant: INTEL CORPORATION
Inventor： Ravi H. Motwani
CPC classification number: G11C13/004 , G06F3/0608 , G06F3/0661 , G06F3/0679 , G11C11/5642 , G11C11/5678 , G11C16/26
Abstract: Embodiments include systems, methods, and apparatuses for reading the signal-level of three-signal-level cells in a non-volatile memory (NVM). In one embodiment, a receiver may be configured to receive a serial string of values and identify which values in the string are the results of a lower-page read or an upper-page read of the cells. In some embodiments, one signal-level of a three-signal level cell may be represented only by a value in the lower-page read of the cells, while a second signal-level of the three-signal level cell may be represented by a value in the lower-page read of the cells and an upper-page read of the cells.
Abstract translation: 实施例包括用于读取非易失性存储器（NVM）中的三信号电平单元的信号电平的系统，方法和装置。 在一个实施例中，接收器可以被配置为接收串行串的值并且识别字符串中的哪些值是小区读取的低页面读取或高字节读取的结果。 在一些实施例中，三信号电平单元的一个信号电平可以仅由单元的较低页面读取中的值表示，而三信号电平单元的第二信号电平可由 单元格的低页面读取中的值和单元格的上页读取。
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公开(公告)号：US12169435B2
公开(公告)日：2024-12-17
申请号：US17171430
申请日：2021-02-09
Applicant: Intel Corporation
Inventor： Debarnab Mitra , Zion S. Kwok , Ravi H. Motwani
Abstract: An embodiment of an electronic apparatus comprises one or more substrates, and logic coupled to the one or more substrates, the logic to detect unreliable messages between check nodes and variable nodes in association with an error correction operation, determine respective degrees of unreliability for the unreliable messages, and reduce an influence of the unreliable messages on the error correction operation, as compared to an influence of reliable messages between the check nodes and the variables nodes, based on the determined respective degrees of unreliability. Other embodiments are disclosed and claimed.
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公开(公告)号：US12032725B2
公开(公告)日：2024-07-09
申请号：US16885726
申请日：2020-05-28
Applicant: Intel Corporation
Inventor： Ravi H. Motwani , Santhosh Kumar Vanaparthy
CPC classification number: G06F21/79 , G06F3/0623 , G06F3/0661 , G06F3/0679 , H04L9/0631 , H04L9/0656 , H04L2209/04
Abstract: Techniques and mechanisms to provide one or more substrates, and logic coupled to the one or more substrates. In an embodiment, the logic is to generate a pseudo-random sequence of bits, and to permute one or more bits of binary unscrambled data. In another embodiment, the logic is further to generate scrambled data based on an exclusive-or operation between the pseudo-random sequence of bits and the permuted data.
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