公开(公告)号：US20180014437A1

公开(公告)日：2018-01-11

申请号：US15712413

申请日：2017-09-22

Applicant: INTEL CORPORATION

Inventor： Robert Sankman

IPC: H05K9/00 ,  H01L23/552

CPC classification number: H05K9/0007 ,  H01L23/552 ,  H01L2224/97 ,  H05K9/006 ,  H05K9/0086

Abstract: Disclosed are EMI shielded packages, electronic device packages, and related methods. EMI shielded packages are formed by applying an insulating material to a first side of a substrate strip, separating the substrate strip into segments, adhering the insulating material of the segments to a solid conductor, applying a conductive paste around lateral sides of the segments, curing the conductive paste, and cutting through the conductive paste and the solid conductor to form the EMI packages. An electronic device package includes a substrate including electronic circuitry, an EMI shield, and an insulating material insulating the substrate from the EMI shield. The EMI shield includes a solid conductor adhered to the insulating material, and a cured conductive paste at least partially surrounding a lateral edge of the substrate. The cured conductive paste electrically connects the solid conductor to a conductive terminal in a lateral side of the substrate.

公开(公告)号：US12272656B2

公开(公告)日：2025-04-08

申请号：US18380022

申请日：2023-10-13

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Robert Sankman ,  Shawna Liff ,  Srinivas Pietambaram ,  Bharat Penmecha

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US12199048B2

公开(公告)日：2025-01-14

申请号：US18397915

申请日：2023-12-27

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Robert Sankman ,  Shawna Liff ,  Srinivas Pietambaram ,  Bharat Penmecha

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US12003023B2

公开(公告)日：2024-06-04

申请号：US16258573

申请日：2019-01-26

Applicant: INTEL CORPORATION

Inventor： Zhenguo Jiang ,  Omkar Karhade ,  Srichaitra Chavali ,  Zhichao Zhang ,  Jimin Yao ,  Stephen Smith ,  Xiaoqian Li ,  Robert Sankman

IPC: H01Q1/22 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/38

CPC classification number: H01Q1/38 ,  H01L21/56 ,  H01L24/26 ,  H01Q1/2283 ,  H05K2201/10098

Abstract: An RF chip package comprises a housing and one or more conductive contacts designed to electrically connect the RF chip package to other conductive contacts. The housing includes a first substrate, a 3-D antenna on the first substrate, and a second substrate. The second substrate includes a plurality of semiconductor devices and is bonded to the first substrate. An interconnect structure allows for electrical connection between the first and second substrates. In some cases, the first substrate is flip-chip bonded to the second substrate or is otherwise connected to the second substrate by an array of solder balls. By integrating both the 3-D antenna and RF circuitry together in the same chip package, costs are minimized while bandwidth is greatly improved compared to a separately machined 3-D antenna.

公开(公告)号：US11756860B2

公开(公告)日：2023-09-12

申请号：US16522443

申请日：2019-07-25

Applicant: Intel Corporation

Inventor： Shrenik Kothari ,  Chandra Mohan Jha ,  Weihua Tang ,  Robert Sankman ,  Xavier Brun ,  Pooya Tadayon

IPC: H01L23/42 ,  H01L23/522 ,  H01L23/373 ,  H01L23/367 ,  H01L25/07 ,  H01L23/538

CPC classification number: H01L23/42 ,  H01L23/367 ,  H01L23/3738 ,  H01L23/522 ,  H01L23/5384 ,  H01L25/072

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

公开(公告)号：US11735533B2

公开(公告)日：2023-08-22

申请号：US16437254

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Robert Sankman ,  Shawna Liff ,  Srinivas Pietambaram ,  Bharat Penmecha

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US11595045B2

公开(公告)日：2023-02-28

申请号：US17359466

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Robert Sankman ,  Ravindranath Mahajan ,  Gregg William Baeckler

IPC: H03K19/1776 ,  H01L25/18 ,  H01L23/367

Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

公开(公告)号：US20190200490A1

公开(公告)日：2019-06-27

申请号：US16290448

申请日：2019-03-01

Applicant: INTEL CORPORATION

Inventor： Robert Sankman

IPC: H05K9/00 ,  H01L23/552

CPC classification number: H05K9/0007 ,  H01L23/552 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K9/006 ,  H05K9/0086

Abstract: Disclosed are EMI shielded packages, electronic device packages, and related methods. EMI shielded packages are formed by applying an insulating material to a first side of a substrate strip, separating the substrate strip into segments, adhering the insulating material of the segments to a solid conductor, applying a conductive paste around lateral sides of the segments, curing the conductive paste, and cutting through the conductive paste and the solid conductor to form the EMI packages. An electronic device package includes a substrate including electronic circuitry, an EMI shield, and an insulating material insulating the substrate from the EMI shield. The EMI shield includes a solid conductor adhered to the insulating material, and a cured conductive paste at least partially surrounding a lateral edge of the substrate. The cured conductive paste electrically connects the solid conductor to a conductive terminal in a lateral side of the substrate.

公开(公告)号：US20170181334A1

公开(公告)日：2017-06-22

申请号：US14974222

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Robert Sankman

IPC: H05K9/00 ,  H01L23/552

CPC classification number: H05K9/0007 ,  H01L23/552 ,  H01L2224/97 ,  H05K9/006 ,  H05K9/0086

Abstract: Disclosed are EMI shielded packages, electronic device packages, and related methods. EMI shielded packages are formed by applying an insulating material to a first side of a substrate strip, separating the substrate strip into segments, adhering the insulating material of the segments to a solid conductor, applying a conductive paste around lateral sides of the segments, curing the conductive paste, and cutting through the conductive paste and the solid conductor to form the EMI packages. An electronic device package includes a substrate including electronic circuitry, an EMI shield, and an insulating material insulating the substrate from the EMI shield. The EMI shield includes a solid conductor adhered to the insulating material, and a cured conductive paste at least partially surrounding a lateral edge of the substrate. The cured conductive paste electrically connects the solid conductor to a conductive terminal in a lateral side of the substrate.

公开(公告)号：US11978689B2

公开(公告)日：2024-05-07

申请号：US18089537

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Shrenik Kothari ,  Chandra Mohan Jha ,  Weihua Tang ,  Robert Sankman ,  Xavier Brun ,  Pooya Tadayon

IPC: H01L23/42 ,  H01L23/367 ,  H01L23/373 ,  H01L23/522 ,  H01L23/00 ,  H01L23/495 ,  H01L23/538 ,  H01L25/07

CPC classification number: H01L23/42 ,  H01L23/367 ,  H01L23/3738 ,  H01L23/522 ,  H01L23/49575 ,  H01L23/5384 ,  H01L24/20 ,  H01L25/072

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.