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公开(公告)号：US09753732B2
公开(公告)日：2017-09-05
申请号：US15175427
申请日：2016-06-07
Applicant: Intel Corporation
Inventor： Xiaowei Jiang , Srihari Makineni , Zhen Fang , Dmitri Pavlov , Ravi Iyer
CPC classification number: G06F9/3806 , G06F9/30058
Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.
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公开(公告)号：US20170048142A1
公开(公告)日：2017-02-16
申请号：US15339354
申请日：2016-10-31
Applicant: Intel Corporation
Inventor： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC: H04L12/741 , H04L29/06
CPC classification number: H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
Abstract translation: 一般来说，一方面，本公开内容描述了一种方法，其包括接收多个入口因特网协议分组，所述多个入口因特网协议分组中的每一个具有因特网协议报头和具有传输控制协议报头和传输控制的传输控制协议段 协议有效载荷，其中属于相同传输控制协议/因特网协议的多个分组流。 该方法还包括准备具有单个因特网协议报头的互联网协议分组和具有单个传输控制协议报头的单个传输控制协议段和由多个因特网协议分组的传输控制协议段有效载荷的组合形成的单个有效载荷 。 该方法还包括产生导致因特网协议分组的接收处理的信号。
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公开(公告)号：US10048743B2
公开(公告)日：2018-08-14
申请号：US15134756
申请日：2016-04-21
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
IPC: G06F1/32 , G06F12/08 , G06F9/44 , H04W88/02 , G06F13/24 , G06F9/50 , G06F9/4401 , H04W52/02 , G06F12/084
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号：US09864427B2
公开(公告)日：2018-01-09
申请号：US15134770
申请日：2016-04-21
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号：US20140223145A1
公开(公告)日：2014-08-07
申请号：US13992797
申请日：2011-12-30
Applicant: INTEL CORPORATION
Inventor： Srihari Makineni , Steven R. King , Zhen Fang , Alexander Redkin , Ravishankar Iyer , Pavel S. Smirnov , Dmitry Gusev , Dmitri Pavlov , May Wu
IPC: G06F9/30
CPC classification number: G06F9/30076 , G06F1/32 , G06F9/30196 , G06F9/3822 , G06F9/3891
Abstract: A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant.
Abstract translation: 处理器可以用仅执行需要完全向后兼容的一些部分指令集的核来构建。 因此，在一些实施例中，可以通过提供仅执行特定指令而不是其他指令的部分核来降低功耗。 不支持的指令可以以其他更节能的方式处理，使得包括部分核心的整体处理器可以完全向后兼容。
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Patent Agency Ranking
16.发明公开公开(公告)号：US20230217253A1
公开(公告)日：2023-07-06
申请号：US17922280
申请日：2021-03-26
Applicant: Intel Corporation
Inventor： Stephen Palermo , Srihari Makineni , Shubha Bommalingaiahnapallya , Rany ElSayed , Lokpraveen Mosur , Neelam Chandwani , Pinkesh Shah , Rajesh Gadiyar , Shrikant M. Shah , Uzair Qureshi
IPC: H04W12/125 , G06F9/50
CPC classification number: H04W12/125 , G06F9/505
Abstract: Systems, methods, and apparatus for workload optimized central processing units are disclosed herein. An example apparatus includes a workload analyzer to determine an application ratio associated with the workload, the application ratio based on an operating frequency to execute the workload, a hardware configurator to configure, before execution of the workload, at least one of (i) one or more cores of the processor circuitry based on the application ratio or (ii) uncore logic of the processor circuitry based on the application ratio, and a hardware controller to initiate the execution of the workload with the at least one of the one or more cores or the uncore logic.
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公开(公告)号：US20200328973A1
公开(公告)日：2020-10-15
申请号：US16870991
申请日：2020-05-10
Applicant: Intel Corporation
Inventor： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC: H04L12/741 , H04L29/06 , H04L12/931
Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
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公开(公告)号：US20160299558A1
公开(公告)日：2016-10-13
申请号：US15134756
申请日：2016-04-21
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号：US20160283244A1
公开(公告)日：2016-09-29
申请号：US15175427
申请日：2016-06-07
Applicant: Intel Corporation
Inventor： Xiaowei Jiang , Srihari Makineni , Zhen Fang , Dmitri Pavlov , Ravi Iyer
CPC classification number: G06F9/3806 , G06F9/30058
Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.
Abstract translation: 根据本发明的一些实施例，用于嵌入式控制器的分支预测单元可以与指令提取单元相关联而不是解码级放置。 另外，分支预测单元也可以不包括分支预测器。 此外，返回地址堆栈可以与指令解码级相关联，并且在结构上与分支预测单元分离。 在某些情况下，这种布置减少了分支预测单元的面积以及功耗。
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公开(公告)号：US09047171B2
公开(公告)日：2015-06-02
申请号：US13631894
申请日：2012-09-29
Applicant: Intel Corporation
Inventor： Zhen Fang , Shih-Lien Lu , Ravishankar Iyer , Srihari Makineni
CPC classification number: G06F11/004 , G06F1/3225 , G06F1/3275 , G06F1/3296 , G11C5/14 , G11C5/141 , Y02D10/13 , Y02D10/14 , Y02D10/172
Abstract: Systems and methods may provide for determining whether a memory access request is error-tolerant, and routing the memory access request to a reliable memory region if the memory access request is error-tolerant. Moreover, the memory access request may be routed to an unreliable memory region if the memory access request is error-tolerant. In one example, use of the unreliable memory region enables a reduction in the minimum operating voltage level for a die containing the reliable and unreliable memory regions.
Abstract translation: 系统和方法可以提供确定存储器访问请求是否是容错的，以及如果存储器访问请求是容错的，则将存储器访问请求路由到可靠的存储器区域。 此外，如果存储器访问请求是容错的，则存储器访问请求可以被路由到不可靠的存储器区域。 在一个示例中，使用不可靠的存储区域使得能够降低包含可靠和不可靠的存储器区域的管芯的最小工作电压电平。
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