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    Providing State Storage in a Processor for System Management Mode
    11.
    发明申请
    Providing State Storage in a Processor for System Management Mode 审中-公开
    在处理器中为系统管理模式提供状态存储

    公开(公告)号：US20170010991A1

    公开(公告)日：2017-01-12

    申请号：US15270151

    申请日：2016-09-20

    Applicant: Intel Corporation

    Inventor： Mahesh Natu ,  Thanunathan Rangarajan ,  Gautam Doshi ,  Shamanna M. Datta ,  Baskaran Ganesan ,  Mohan J. Kumar ,  Rajesh S. Parthasarathy ,  Frank Binns ,  Rajesh Nagaraja Murthy ,  Robert C. Swanson

    IPC: G06F13/24 ,  G11C7/10 ,  G11C11/406

    CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/461 ,  G11C7/1072 ,  G11C11/40615

    Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的体系结构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。

    PROTECTION SCHEME FOR REMOTELY-STORED DATA
    13.
    发明申请
    PROTECTION SCHEME FOR REMOTELY-STORED DATA 有权
    远程存储数据保护方案

    公开(公告)号：US20150220745A1

    公开(公告)日：2015-08-06

    申请号：US14358789

    申请日：2013-09-27

    Applicant: INTEL CORPORATION

    Inventor： Hariprasad Nellitheertha ,  Deepak S. ,  Thanunathan Rangarajan ,  Anil S. Keshavamurthy

    IPC: G06F21/60 ,  G06F9/455

    CPC classification number: G06F21/602 ,  G06F9/45558 ,  G06F15/16 ,  G06F21/53 ,  G06F21/60 ,  G06F21/6218 ,  G06F2009/45587

    Abstract: The present disclosure is directed to a protection scheme for remotely-stored data. A system may comprise, for example, at least one device including at least one virtual machine (VM) and a trusted execution environment (TEE). The TEE may include an encryption service to encrypt or decrypt data received from the at least one VM. In one embodiment, the at least one VM may include an encryption agent to interact with interfaces in the encryption service. For example, the encryption agent may register with the encryption service, at which time an encryption key corresponding to the at least one VM may be generated. After verifying the registration of the encryption agent, the encryption service may utilize the encryption key corresponding to the at least one VM to encrypt or decrypt data received from the encryption agent. The encryption service may then return the encrypted or decrypted data to the encryption agent.

    Abstract translation: 本公开涉及用于远程存储的数据的保护方案。 系统可以包括例如至少一个包括至少一个虚拟机（VM）和可信执行环境（TEE）的设备。 TEE可以包括加密或加密从至少一个VM接收的数据的加密服务。 在一个实施例中，所述至少一个VM可以包括与加密服务中的接口交互的加密代理。 例如，加密代理可以向加密服务注册，此时可以生成与至少一个VM相对应的加密密钥。 在验证加密代理的注册之后，加密服务可以利用与至少一个VM相对应的加密密钥来加密或解密从加密代理接收的数据。 加密服务然后可以将加密或解密的数据返回给加密代理。

    MEMORY POISONING WITH HINTS
    14.
    发明申请
    MEMORY POISONING WITH HINTS 审中-公开

    公开(公告)号：US20190138378A1

    公开(公告)日：2019-05-09

    申请号：US16235922

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Thanunathan Rangarajan

    IPC: G06F11/00 ,  G06F11/07

    Abstract: A method and system for storing hints in poisoned data of a computer system memory includes receiving poisoned data in a component of the system; forwarding the poisoned data to a memory controller of the system; and forwarding additional data regarding the poisoned data to a memory controller. The memory controller writes the poisoned data to the system memory wherein the written poisoned data includes a poison signature and a hint based on the additional data regarding the poisoned data; and when the written poisoned data is read signaling a system error and returning the poison signature and the hint to a system software of the system.

    METHOD, SYSTEM, AND APPARATUS FOR AN IMPROVED MEMORY ERROR PREDICTION SCHEME
    15.
    发明申请
    METHOD, SYSTEM, AND APPARATUS FOR AN IMPROVED MEMORY ERROR PREDICTION SCHEME 审中-公开

    公开(公告)号：US20190129777A1

    公开(公告)日：2019-05-02

    申请号：US16082512

    申请日：2017-02-16

    Applicant: Intel Corporation

    Inventor： Thanunathan Rangarajan

    IPC: G06F11/07 ,  G06F11/10

    Abstract: Method, system, and apparatus for predicting imminent memory failures based on one or more adverse conditions being subjected to the memory. One embodiment of a method comprises: tracking one or more corrected memory errors (CEs) in a memory; tracking one or more generated tokens, wherein the tokens are being generated at an initial rate; detecting one or more adverse conditions being subjected to the memory and responsive to the detection, reduce the rate at which the tokens are being generated; decrementing the tracked CEs based on a reoccurring leak timer, wherein upon each expiration of the reoccurring leak timer, the tracked CEs is decremented by one so long as there is at least one tracked token; reducing the tracked tokens by one in response to the decrement of the tracked CEs; and triggering a CE overflow signal upon detecting a count of the tracked CEs exceeding an overflow limit.

    Memory poisoning with hints
    16.
    发明授权
    Memory poisoning with hints 有权

    公开(公告)号：US10025647B2

    公开(公告)日：2018-07-17

    申请号：US13709290

    申请日：2012-12-10

    Applicant: Intel Corporation

    Inventor： Thanunathan Rangarajan

    IPC: G06F11/00 ,  G06F11/07

    Abstract: A method and system for storing hints in poisoned data of a computer system memory includes receiving poisoned data in a component of the system; forwarding the poisoned data to a memory controller of the system; and forwarding additional data regarding the poisoned data to a memory controller. The memory controller writes the poisoned data to the system memory wherein the written poisoned data includes a poison signature and a hint based on the additional data regarding the poisoned data; and when the written poisoned data is read signaling a system error and returning the poison signature and the hint to a system software of the system.

    Protection scheme for remotely-stored data
    17.
    发明授权
    Protection scheme for remotely-stored data 有权

    公开(公告)号：US09852299B2

    公开(公告)日：2017-12-26

    申请号：US14358789

    申请日：2013-09-27

    Applicant: INTEL CORPORATION

    Inventor： Hariprasad Nellitheertha ,  Deepak S. ,  Thanunathan Rangarajan ,  Anil S. Keshavamurthy

    IPC: G06F21/60 ,  G06F15/16 ,  G06F21/62 ,  G06F9/455 ,  G06F21/53

    CPC classification number: G06F21/602 ,  G06F9/45558 ,  G06F15/16 ,  G06F21/53 ,  G06F21/60 ,  G06F21/6218 ,  G06F2009/45587

    Abstract: The present disclosure is directed to a protection scheme for remotely-stored data. A system may comprise, for example, at least one device including at least one virtual machine (VM) and a trusted execution environment (TEE). The TEE may include an encryption service to encrypt or decrypt data received from the at least one VM. In one embodiment, the at least one VM may include an encryption agent to interact with interfaces in the encryption service. For example, the encryption agent may register with the encryption service, at which time an encryption key corresponding to the at least one VM may be generated. After verifying the registration of the encryption agent, the encryption service may utilize the encryption key corresponding to the at least one VM to encrypt or decrypt data received from the encryption agent. The encryption service may then return the encrypted or decrypted data to the encryption agent.

    Electrical margining of multi-parameter high-speed interconnect links with multi-sample probing
    19.
    发明授权
    Electrical margining of multi-parameter high-speed interconnect links with multi-sample probing 有权

    公开(公告)号：US09817054B2

    公开(公告)日：2017-11-14

    申请号：US13729756

    申请日：2012-12-28

    Applicant: Intel Corporation

    Inventor： Thanunathan Rangarajan ,  Shreesh Chhabbi ,  Arvind A. Kumar ,  Venkatraman Iyer

    IPC: G01R31/04 ,  G01R31/30

    CPC classification number: G01R31/04 ,  G01R31/30

    Abstract: Methods and apparatus relating to electrical margining of multi-parameter high-speed interconnect links with multi-sample probing are described. In one embodiment, logic is provided to generate one or more parameter values, corresponding to an electrical operating margin of an interconnect. The one or more parameter values are generated based on a plurality of eye observation sets to be detected in response to operation of the interconnect in accordance with a plurality of parameter sets (e.g., by using quantitative optimization techniques). In turn, the interconnect is to be operated at the one or more parameter values if it is determined that the one or more parameter values cause the interconnect to operate at an optimum level relative to an operation of the interconnect in accordance with one or more less optimum parameter levels. Other embodiments are also disclosed and claimed.

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