公开(公告)号：US11152461B2

公开(公告)日：2021-10-19

申请号：US15983540

申请日：2018-05-18

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Anupama Bowonder ,  Biswajeet Guha ,  Tahir Ghani ,  Stephen M. Cea ,  William Hsu ,  Szuya S Liao ,  Pratik A. Patel

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“Rext”) of the semiconductor device.

公开(公告)号：US20190355811A1

公开(公告)日：2019-11-21

申请号：US15983540

申请日：2018-05-18

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Anupama Bowonder ,  Biswajeet Guha ,  Tahir Ghani ,  Stephen M. Cea ,  William Hsu ,  SZUYA S. LIAO ,  PRATIK A. PATEL

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“Rext”) of the semiconductor device.

公开(公告)号：US12224350B2

公开(公告)日：2025-02-11

申请号：US18374959

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Leonard P. Guler ,  Dax M. Crum ,  Tahir Ghani

IPC: H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

公开(公告)号：US20240071831A1

公开(公告)日：2024-02-29

申请号：US17896813

申请日：2022-08-26

Applicant: INTEL CORPORATION

Inventor： Chang Wan Han ,  Biswajeet Guha ,  Vivek Thirtha ,  William Hsu ,  Ian Yang ,  Oleg Golonzka ,  Kevin J. Fischer ,  Suman Dasgupta ,  Sameerah Desnavi ,  Deepak Sridhar

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696

Abstract: An integrated circuit includes laterally adjacent first and second devices. The first device includes a first source or drain region, a first gate structure, and a first inner spacer between the first source or drain region and the first gate structure. The second device includes a second source or drain region, a second gate structure, and a second inner spacer between the second source or drain region and the second gate structure. In an example, the first source or drain region has a width that is at least 1 nanometer different from a width of the second source or drain region, and/or the first inner spacer has a width that is at least 1 nanometer different from a width of the second inner spacer. The various widths are measured in a direction of a semiconductor body between the first source or drain region and the first gate structure

公开(公告)号：US11901458B2

公开(公告)日：2024-02-13

申请号：US17850799

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Bruce E. Beattie ,  Leonard Guler ,  Biswajeet Guha ,  Jun Sung Kang ,  William Hsu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/6681 ,  H01L29/66545 ,  H01L2029/7858

Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.

公开(公告)号：US20230420574A1

公开(公告)日：2023-12-28

申请号：US17847555

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Ashish Agrawal ,  Jack T. Kavalieros ,  Rambert Nahm ,  Natalie Briggs ,  Susmita Ghose ,  Glenn Glass ,  Devin R. Merrill ,  Aaron A. Budrevich ,  Shruti Subramanian ,  Biswajeet Guha ,  William Hsu ,  Adedapo A. Oni ,  Rahul Ramamurthy ,  Anupama Bowonder ,  Hsin-Ying Tseng ,  Rajat K. Paul ,  Marko Radosavljevic

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392

Abstract: Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.

公开(公告)号：US11855223B2

公开(公告)日：2023-12-26

申请号：US17549827

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Leonard P. Guler ,  Dax M. Crum ,  Tahir Ghani

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7856 ,  H01L21/02603 ,  H01L21/823481 ,  H01L23/5226 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/42392 ,  H01L2029/7858

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

公开(公告)号：US11824116B2

公开(公告)日：2023-11-21

申请号：US16719222

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Ayan Kar ,  Nicholas Thomson ,  Benjamin Orr ,  Nathan Jack ,  Kalyan Kolluru ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7831 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/785

Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.

公开(公告)号：US11799009B2

公开(公告)日：2023-10-24

申请号：US16716907

申请日：2019-12-17

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L29/42392 ,  H01L27/0886 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US11749733B2

公开(公告)日：2023-09-05

申请号：US17691926

申请日：2022-03-10

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Biswajeet Guha ,  Mark Armstrong ,  William Hsu ,  Tahir Ghani ,  Swaminathan Sivakumar

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L27/0886 ,  H01L29/16 ,  H01L29/20 ,  H01L29/785

Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.