中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

102 records (took 0.02 seconds)

    INLINE MEASUREMENT OF THROUGH-SILICON VIA DEPTH
    12.
    发明申请
    INLINE MEASUREMENT OF THROUGH-SILICON VIA DEPTH 有权
    通过深度通过硅片进行在线测量

    公开(公告)号：US20150187667A1

    公开(公告)日：2015-07-02

    申请号：US14643436

    申请日：2015-03-10

    Applicant: International Business Machines Corporation

    Inventor： Hanyi Ding ,  J. Edwin Hostetter ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC: H01L21/66 ,  H01L21/304

    CPC classification number: H01L22/26 ,  H01L21/304 ,  H01L22/14 ,  H01L22/34

    Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.

    Abstract translation: 公开了一种通过硅通孔（TSV）电容测试结构和基于电容确定TSV深度的方法。 TSV电容测试结构由均匀间隔的多个TSV条形成。 第一组电杆电连接以形成第一电容器节点，并且第二组电杆电连接以形成第二电容器节点。 测量电容，并在背面变薄之前计算TSV深度。 然后计算的TSV深度可以被馈送到下游研磨和/或抛光工具以控制背面变薄处理，使得半导体晶片变薄使得背面与TSV齐平。

    PRESSURE SENSING AND CONTROL FOR SEMICONDUCTOR WAFER PROBING
    14.
    发明申请
    PRESSURE SENSING AND CONTROL FOR SEMICONDUCTOR WAFER PROBING 有权
    用于半导体波形探测的压力感测和控制

    公开(公告)号：US20150145544A1

    公开(公告)日：2015-05-28

    申请号：US14560138

    申请日：2014-12-04

    Applicant: International Business Machines Corporation

    Inventor： Robert D. Edwards ,  Oleg Gluschenkov ,  Louis V. Medina ,  Tso-Hui Ting ,  Ping-Chuan Wang ,  Yongchun Xin

    IPC: G01R1/067 ,  G01R1/073

    CPC classification number: G01R31/2891 ,  G01R1/06794 ,  G01R1/07364

    Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.

    Abstract translation: 晶片探测系统包括探针卡组件，其具有构造成与安装在马达驱动晶片卡盘上的半导体晶片接触的多个单独的探针结构，每个探针结构配置有与其集成的压力感测单元; 以及控制器，被配置为用一个或多个压电驱动器单元来驱动探针卡组件，以响应来自各个探针结构的压力感测单元的反馈。

    INTEGRATED CIRCUIT STRUCTURE WITH THROUGH-SEMICONDUCTOR VIA
    15.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE WITH THROUGH-SEMICONDUCTOR VIA 有权
    通过半导体的集成电路结构

    公开(公告)号：US20150115460A1

    公开(公告)日：2015-04-30

    申请号：US14065454

    申请日：2013-10-29

    Applicant: International Business Machines Corporation

    Inventor： Fen Chen ,  Minhua Lu ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

    IPC: H01L23/48 ,  H01L23/522

    CPC classification number: H01L23/481 ,  H01L23/5226 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure generally provides for integrated circuit (IC) structures with through-semiconductor vias (TSV). In an embodiment, an IC structure may include a through-semiconductor via (TSV) embedded in a substrate, the TSV having a cap; a dielectric layer adjacent to the substrate; a metal layer adjacent to the dielectric layer; a plurality of vias each embedded within the dielectric layer and coupling the metal layer to the cap of the TSV at respective contact points, wherein the plurality of vias is configured to create a substantially uniform current density throughout the TSV.

    Abstract translation: 本公开通常提供具有贯穿半导体通孔（TSV）的集成电路（IC）结构。 在一个实施例中，IC结构可以包括嵌入在衬底中的贯穿半导体通孔（TSV），TSV具有帽; 与基板相邻的电介质层; 与介电层相邻的金属层; 多个通孔，每个通孔嵌入在电介质层内，并将金属层耦合到各个接触点处的TSV的盖，其中多个通孔被配置成在整个TSV中产生基本均匀的电流密度。

    INTERCONNECT WITH HYBRID METALLIZATION
    16.
    发明申请
    INTERCONNECT WITH HYBRID METALLIZATION 有权
    与混合金属化相互连接

    公开(公告)号：US20140332963A1

    公开(公告)日：2014-11-13

    申请号：US13890560

    申请日：2013-05-09

    Applicant: International Business Machines Corporation

    Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Lijuan Zhang

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An electronic interconnect structure having a hybridized metal structure near regions of high operating temperature on an integrated circuit, and methods of making the same. The hybridized metal structure features at least two different metals in a single metallization level. The first metal is in a region of high operating temperature and the second region is in a region of normal operating temperatures. In a preferred embodiment the first metal includes aluminum and is in a first level metallization over an active area of the device while the second metal includes copper. In some embodiments, the first and second metals are not in direct physical contact. In other embodiments the first and second metals physically contact each other. In a preferred embodiment, a top surface of the first metal is not co-planar with a top surface of the second metal, despite being in the same metallization level.

    Abstract translation: 一种在集成电路上具有高工作温度区域附近的杂化金属结构的电子互连结构及其制造方法。 杂化金属结构在单一金属化水平中具有至少两种不同的金属。 第一金属处于高工作温度的区域，第二区域处于正常工作温度的区域。 在优选实施例中，第一金属包括铝，并且在器件的有效区域上处于第一级金属化，而第二金属包括铜。 在一些实施例中，第一和第二金属不是直接的物理接触。 在其他实施例中，第一和第二金属物理地彼此接触。 在优选实施例中，尽管处于相同的金属化水平，第一金属的顶表面与第二金属的顶表面不共面。

Patent Agency Ranking