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公开(公告)号：US20150170996A1
公开(公告)日：2015-06-18
申请号：US14132287
申请日：2013-12-18
Applicant: International Business Machines Corporation
Inventor： Dulce M. Altabella Lazzi , Wiren D. Becker , Jinwoo Choi , Rohan U. Mandrekar
IPC: H01L23/48 , H01L21/768
CPC classification number: H01L23/50 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L2224/16225 , H01L2924/0002 , H01L2924/15174 , H01L2924/15311 , H05K1/0222 , H05K1/0225 , H05K1/116 , H05K2201/09309 , H05K2201/09681 , H01L2924/00
Abstract: In some embodiments, a multi-layered package includes a plurality of mesh planes. The multi-layered package includes at least one through-mesh-plane via positioned to traverse the plurality of mesh planes, wherein the at least one through-mesh-plane via is to intersect the plurality of mesh planes. The multi-layered package includes at least one signal via positioned to traverse the plurality of mesh planes, wherein the at least one signal via is positioned within an opening of the plurality of mesh planes and is positioned adjacent to the at least one through through-mesh-plane via.
Abstract translation: 在一些实施例中，多层包装包括多个网格平面。 所述多层封装包括至少一个贯穿所述多个网格平面的通孔平面通路，其中所述至少一个通孔平面通孔与所述多个网格平面相交。 所述多层封装包括至少一个经过定位以穿过所述多个网格平面的信号，其中所述至少一个信号通孔定位在所述多个网格平面的开口内，并且被定位成与所述至少一个通孔相邻， 网格平面通孔。
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公开(公告)号：US09972566B2
公开(公告)日：2018-05-15
申请号：US15336884
申请日：2016-10-28
Applicant: International Business Machines Corporation
Inventor： Zhaoqing Chen , Matteo Cocchini , Rohan U. Mandrekar , Tingdong Zhou
IPC: H01L23/498 , H01L23/528 , H04B3/32 , H01P3/02 , H01P3/08 , H05K1/02 , H04B1/00 , H01L23/66
CPC classification number: H01L23/49838 , H01L23/528 , H01L23/66 , H01L2223/6627 , H01P3/02 , H01P3/026 , H01P3/081 , H04B1/00 , H04B3/32 , H05K1/0216 , H05K1/0245
Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.
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公开(公告)号：US09646925B2
公开(公告)日：2017-05-09
申请号：US14824125
申请日：2015-08-12
Applicant: International Business Machines Corporation
Inventor： Zhaoqing Chen , Matteo Cocchini , Rohan U. Mandrekar , Tingdong Zhou
IPC: H01L23/498 , H01L23/528 , H04B3/32 , H01P3/02 , H01P3/08 , H05K1/02 , H04B1/00
CPC classification number: H01L23/49838 , H01L23/528 , H01L23/66 , H01L2223/6627 , H01P3/02 , H01P3/026 , H01P3/081 , H04B1/00 , H04B3/32 , H05K1/0216 , H05K1/0245
Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.
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公开(公告)号：US20160149611A1
公开(公告)日：2016-05-26
申请号：US14824125
申请日：2015-08-12
Applicant: International Business Machines Corporation
Inventor： Zhaoqing Chen , Matteo Cocchini , Rohan U. Mandrekar , Tingdong Zhou
IPC: H04B3/32
CPC classification number: H01L23/49838 , H01L23/528 , H01L23/66 , H01L2223/6627 , H01P3/02 , H01P3/026 , H01P3/081 , H04B1/00 , H04B3/32 , H05K1/0216 , H05K1/0245
Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.
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15.发明申请公开(公告)号：US20140075749A1
公开(公告)日：2014-03-20
申请号：US14089084
申请日：2013-11-25
Applicant: International Business Machines Corporation
Inventor： Douglas A. Baska , Daniel M. Dreps , Rohan U. Mandrekar , Roger D. Weekly
CPC classification number: H05K3/4623 , H05K1/0216 , H05K1/141 , H05K3/368 , H05K2201/10189 , Y10T29/49126 , Y10T29/49162 , Y10T29/53004
Abstract: Some embodiments of the inventive subject matter are directed to forming, on a first circuit board, first pins that connect to first leads of a first electronic component; forming, on the first circuit board, second pins that connect to second leads of a second electronic component; affixing the first circuit board to a second circuit board having a first layer with first wires; and forming second wires on a second layer of the second circuit board, wherein said forming the second wires creates an electrical connection on the second circuit board between a portion of the first pins and a portion of the second pins. In some embodiments, the second circuit board is smaller than the first circuit board, and the second layer of the second circuit board is, in length, approximately equivalent to a distance between the first electronic component and the second electronic component.
Abstract translation: 本发明的一些实施例涉及在第一电路板上形成连接到第一电子部件的第一引线的第一引脚; 在第一电路板上形成连接到第二电子部件的第二引线的第二引脚; 将第一电路板固定到具有第一电线的第一电路板的第二电路板; 以及在所述第二电路板的第二层上形成第二电线，其中所述形成所述第二电线在所述第二电路板上在所述第一引脚的一部分和所述第二引脚的一部分之间产生电连接。 在一些实施例中，第二电路板小于第一电路板，并且第二电路板的第二层的长度大致等于第一电子部件和第二电子部件之间的距离。
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Patent Agency Ranking
公开(公告)号：US20180352662A1
公开(公告)日：2018-12-06
申请号：US16038417
申请日：2018-07-18
Applicant: International Business Machines Corporation
Inventor： Douglas A. Baska , Daniel M. Dreps , Rohan U. Mandrekar , Roger D. Weekly
CPC classification number: H05K3/4623 , H05K1/0216 , H05K1/141 , H05K3/368 , H05K2201/10189 , Y10T29/49126 , Y10T29/49162 , Y10T29/53004
Abstract: Some embodiments of the inventive subject matter are directed to forming, on a first circuit board, first pins that connect to first leads of a first electronic component; forming, on the first circuit board, second pins that connect to second leads of a second electronic component; affixing the first circuit board to a second circuit board having a first layer with first wires; and forming second wires on a second layer of the second circuit board, wherein said forming the second wires creates an electrical connection on the second circuit board between a portion of the first pins and a portion of the second pins. In some embodiments, the second circuit board is smaller than the first circuit board, and the second layer of the second circuit board is, in length, approximately equivalent to a distance between the first electronic component and the second electronic component.
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公开(公告)号：US09543241B2
公开(公告)日：2017-01-10
申请号：US14551185
申请日：2014-11-24
Applicant: International Business Machines Corporation
Inventor： Zhaoqing Chen , Matteo Cocchini , Rohan U. Mandrekar , Tingdong Zhou
IPC: H01L23/498 , H01L23/528 , H04B3/32 , H01P3/02 , H01P3/08 , H05K1/02 , H04B1/00
CPC classification number: H01L23/49838 , H01L23/528 , H01L23/66 , H01L2223/6627 , H01P3/02 , H01P3/026 , H01P3/081 , H04B1/00 , H04B3/32 , H05K1/0216 , H05K1/0245
Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.
Abstract translation: 包括多个互连件的电子设备以网格图案正交布置并均匀间隔第一距离，所述多个互连件包括：第一导体对，其具有沿第一方向彼此相邻布置的导体，所述第一方向定向 相对于正交栅格图案的对角线的第二导体对，具有基本上垂直于第一方向的第二方向彼此相邻布置的导体的第二导体对，第二导体对的每个导体与第一导体对的每个信号导体间隔开第一距离 导体对和第三导体对，其中导体在基本上平行于第一方向的第三方向上彼此相邻布置，第三导体对的每个导体与第二导体对的信号元件之一间隔开第一距离 。
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公开(公告)号：US09456506B2
公开(公告)日：2016-09-27
申请号：US14136135
申请日：2013-12-20
Applicant: International Business Machines Corporation
Inventor： John L. Colbert , Daniel M. Dreps , Paul M. Harvey , Rohan U. Mandrekar
CPC classification number: H05K3/325 , G06F1/183 , G06F1/20 , H01L23/36 , H01L23/49827 , H01L25/105 , H01L2225/107 , H01L2924/15313 , H05K7/1061 , Y10T29/49128 , Y10T29/49169
Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.
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公开(公告)号：US09445507B2
公开(公告)日：2016-09-13
申请号：US14731815
申请日：2015-06-05
Applicant: International Business Machines Corporation
Inventor： John L. Colbert , Daniel M. Dreps , Paul M. Harvey , Rohan U. Mandrekar
CPC classification number: H05K3/325 , G06F1/183 , G06F1/20 , H01L23/36 , H01L23/49827 , H01L25/105 , H01L2225/107 , H01L2924/15313 , H05K7/1061 , Y10T29/49128 , Y10T29/49169
Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.
Abstract translation: 提供了一种用于打包多个套接字，一跳对称多处理器拓扑的机制。 该机构经由第一多个平面栅格阵列（LGA）连接器中的相应一个将第一多个处理器模块中的每一个连接到第一多插槽平面。 该机构经由第二多个LGA连接器将第一多插槽平面连接到再分配卡的第一侧。 该机构经由第三多个LGA连接器中的相应一个将第二多个处理器模块中的每一个连接到第二多插槽平面。 该机构经由第四多个LGA连接器将第二多插槽平面连接到再分配卡的第二侧。
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公开(公告)号：US09232646B2
公开(公告)日：2016-01-05
申请号：US14102832
申请日：2013-12-11
Applicant: International Business Machines Corporation
Inventor： Jinwoo Choi , Daniel M. Dreps , Rohan U. Mandrekar
IPC: H01L23/528 , H05K1/02 , C04B37/00 , H05K1/03 , H05K3/46 , H01L21/48 , H05K3/12 , H01L23/522 , H05K1/09 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/24
CPC classification number: H05K1/0298 , B32B18/00 , C04B37/006 , C04B2237/34 , C04B2237/343 , C04B2237/366 , C04B2237/68 , H01L21/4857 , H01L21/486 , H01L21/4867 , H01L23/13 , H01L23/49822 , H01L23/49827 , H01L23/50 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L2924/0002 , H05K1/0245 , H05K1/0306 , H05K1/092 , H05K3/005 , H05K3/1216 , H05K3/1233 , H05K3/1291 , H05K3/245 , H05K3/4667 , H05K2201/0338 , H05K2201/035 , H05K2201/09272 , H05K2201/09709 , H05K2203/0126 , H05K2203/063 , Y10T156/10 , H01L2924/00
Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating differential wiring patterns in multilayer glass-ceramic (MLC) modules. A structure and method of forming a MLC having layers with staggered, or offset, pairs of lines formed directly on one another are disclosed. In addition, a structure and method of forming a MLC having layers with staggered, or offset, pairs of lines that periodically reverse polarity are disclosed.
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