公开(公告)号：US20250006663A1

公开(公告)日：2025-01-02

申请号：US18216923

申请日：2023-06-30

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander POLOMOFF ,  Terence Hook ,  Matthew Stephen Angyal ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Kisik Choi ,  FEE LI LIE ,  Ruilong Xie ,  LEI ZHUANG

IPC: H01L23/58 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first layers; a plurality of second dielectric layers at a top side of the device layer; first and second sense pads; and a metal body that electrically connects the pads. The metal body includes a first portion that is embedded in the first layers, made of a first plurality of discrete segments; a second portion that is embedded in the second layers, made of a second plurality of discrete segments, of which a first is electrically connected to the first pad and a second is electrically connected to the second pad; and a plurality of vias that interconnect the first and second portions. Breaking any of the vias reduces the electrical connectivity between the pads.

公开(公告)号：US20250006629A1

公开(公告)日：2025-01-02

申请号：US18216978

申请日：2023-06-30

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander POLOMOFF ,  Terence Hook ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Matthew Stephen Angyal ,  FEE LI LIE ,  Ruilong Xie ,  LEI ZHUANG ,  Kisik Choi

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/60

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first layers; a plurality of second dielectric layers at a top side of the device layer; first and second sense pads at a top side of the second layers; a first metal body electrically connected to the first pad; and a second metal body electrically connected to the second pad. The bodies, with the layers, form a capacitor that couples the pads. Each of the bodies includes: an upper portion that is embedded in the plurality of second layers and is directly connected to a respective one of the first and second pads; a lower portion that is embedded in the plurality of first layers; and a via that connects the upper to the lower portion through the active layer.

公开(公告)号：US20240429178A1

公开(公告)日：2024-12-26

申请号：US18211669

申请日：2023-06-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Alexander Polomoff ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Matthew Stephen Angyal ,  Fee Li Lie ,  Ruilong Xie ,  Terence Hook

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/58

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a back end of the line (BEOL) stack including a dielectric stack, and an active device region in the dielectric stack, the active device region including at least one component selected from the group consisting of transistors, capacitors and nanosheet structures; and a crack stop that extends vertically through the active device region.

公开(公告)号：US20230378258A1

公开(公告)日：2023-11-23

申请号：US17663676

申请日：2022-05-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Anthony I. Chou ,  Brent A. Anderson ,  John Christopher Arnold ,  Junli Wang ,  Kai Zhao ,  Terence Hook ,  Julien Frougier ,  Xuefeng Liu

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/02 ,  H01L21/74

CPC classification number: H01L29/0665 ,  H01L21/76898 ,  H01L21/0237 ,  H01L21/0259 ,  H01L21/76829 ,  H01L21/743

Abstract: A method including forming an oxide layer on a first substrate and forming a second substrate on the oxide layer. Doping a first section of the second substrate while not doping a second section of the second substrate. Forming a first nano device on the second section of the second substrate and forming a second nano device on first section of the second substrate. Flipping the first substrate over to allow for backside processing of the substrate and forming at least one backside contact connected to the first nano device while backside contacts are not formed or connected to the second nano device.

公开(公告)号：US10586854B2

公开(公告)日：2020-03-10

申请号：US15975869

申请日：2018-05-10

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael A. Guillorn ,  Terence Hook ,  Robert R. Robison ,  Reinaldo Vega ,  Tenko Yamashita

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/786

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

公开(公告)号：US20180308945A1

公开(公告)日：2018-10-25

申请号：US15975869

申请日：2018-05-10

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael A. Guillorn ,  Terence Hook ,  Robert R. Robison ,  Reinaldo Vega ,  Tenko Yamashita

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

公开(公告)号：US20250006590A1

公开(公告)日：2025-01-02

申请号：US18216887

申请日：2023-06-30

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander POLOMOFF ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Matthew Stephen Angyal ,  Ruilong Xie ,  FEE LI LIE ,  Kisik Choi ,  Terence Hook ,  LEI ZHUANG

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/60 ,  H01L25/065 ,  H01L29/06

Abstract: An exemplary structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first dielectric layers; a plurality of second dielectric layers at a top side of the active device layer; and a metal body. The body includes a first portion that is embedded in the plurality of first dielectric layers. The first portion comprises a first layer of first metal. The body further includes a second portion that is embedded in the plurality of second dielectric layers. The second portion comprises a first layer of second metal. A plurality of vias interconnect the first portion to the second portion through the active device layer. The first layer of the first portion mechanically connects the plurality of vias and the first layer of the second portion mechanically connects the plurality of vias.

公开(公告)号：US20240379658A1

公开(公告)日：2024-11-14

申请号：US18195701

申请日：2023-05-10

Applicant: International Business Machines Corporation

Inventor： Terence Hook ,  Anthony I. Chou

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/861

Abstract: A semiconductor structure including a stacked FET vertical diode is provided. The stacked FET vertical diode includes vertically stacked source/drain regions of opposite conductivity that are electrically connected by a semiconductor material layer that is positioned between the vertically stacked source/drain regions.

公开(公告)号：US20240203816A1

公开(公告)日：2024-06-20

申请号：US18067207

申请日：2022-12-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kisik Choi ,  Nicholas Alexander POLOMOFF ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Ruilong Xie ,  Terence Hook ,  Matthew Angyal ,  FEE LI LIE

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/367 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L23/3735 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/80006 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80447 ,  H01L2924/0504 ,  H01L2924/0544

Abstract: Semiconductor devices and methods of forming the same include a front-end-of-line (FEOL) layer. A back-end-of-line (BEOL) layer includes a thermal transfer structure in contact with the FEOL layer. A carrier wafer is bonded to the BEOL layer and includes a thermal dissipation structure in contact with the thermal transfer structure.

公开(公告)号：US20240096871A1

公开(公告)日：2024-03-21

申请号：US17947524

申请日：2022-09-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Terence Hook ,  Junli Wang ,  Miaomiao Wang

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0292

Abstract: An integrated circuit is presented including a protection diode including a plurality of first gates and a plurality of first source/drain (S/D) contacts and a device under test (DUT) including a plurality of second gates and a plurality of second S/D contacts, the DUT being electrically connected to the protection diode by either at least one gate contact or at least on CA contact or at least one buried power rail (BPR). The protection diode is electrically connected to the DUT by middle-of-line (MOL) layers for gate oxide protection before M1 formation.