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公开(公告)号：US20180113969A1
公开(公告)日：2018-04-26
申请号：US15626582
申请日：2017-06-19
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Qianwen Chen , Li-Wen Hung , Wanki Kim , John U. Knickerbocker , Kenneth P. Rodbell , Robert L. Wisnieff
CPC classification number: G06F17/5027 , G06F15/7803 , G06F15/7807 , G06F15/7857 , G06F15/803 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L24/17 , H01L25/065 , H01L25/0655 , H01L25/071 , H01L25/112 , H01L25/115 , H01L25/18 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2221/68368 , H01L2221/68381 , H01L2224/08225 , H01L2224/11002 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/80006 , H01L2224/81005 , H01L2924/1205 , H01L2924/1206 , H01L2924/13051 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1421 , H01L2924/1432 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105
Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.
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公开(公告)号：US20160125938A1
公开(公告)日：2016-05-05
申请号：US14749161
申请日：2015-06-24
Applicant: International Business Machines Corporation
Inventor： Matthew J. BrightSky , SangBum Kim , Wanki Kim , Chung H. Lam
CPC classification number: G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2013/0078 , G11C2013/0083 , G11C2013/0092 , H01L45/06 , H01L45/144
Abstract: A memory device that includes a phase change material. The phase change material is programmable to a metastable set state and metastable reset state. Furthermore, the phase change material includes an initial state with an initial electrical resistance between the set electrical resistance and the reset electrical resistance. The initial state is at a lower potential energy than the set state and the reset state. Thus, the electrical resistance of the phase change material programmed to the set state or the reset state drifts toward the initial electrical resistance over time. The memory device also includes a first electrode electrically coupled to a first area of the phase change material, and a second electrode electrically coupled to a second area of the phase change material.
Abstract translation: 一种包括相变材料的存储器件。 相变材料可编程为亚稳态和亚稳态复位状态。 此外，相变材料包括在设定的电阻和复位电阻之间具有初始电阻的初始状态。 初始状态处于比设定状态和复位状态低的势能。 因此，被编程到设定状态或复位状态的相变材料的电阻随时间漂移到初始电阻。 存储器件还包括电耦合到相变材料的第一区域的第一电极和电耦合到相变材料的第二区域的第二电极。
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公开(公告)号：US11437571B2
公开(公告)日：2022-09-06
申请号：US16451178
申请日：2019-06-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Wanki Kim , Fabio Carta , Chung H. Lam , Robert L. Bruce
Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.
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14.发明申请公开(公告)号：US20200019732A1
公开(公告)日：2020-01-16
申请号：US16578321
申请日：2019-09-21
Applicant: International Business Machines Corporation
Inventor： Richard H. Boivie , Eduard A. Cartier , Daniel J. Friedman , Kohji Hosokawa , Charanjit Jutla , Wanki Kim , Chandrasekara Kothandaraman , Chung Lam , Frank R. Libsch , Seiji Munetoh , Ramachandran Muralidhar , Vijay Narayanan , Dirk Pfeiffer , Devendra K. Sadana , Ghavam G. Shahidi , Robert L. Wisnieff
Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
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15.发明授权公开(公告)号：US10423805B2
公开(公告)日：2019-09-24
申请号：US15389078
申请日：2016-12-22
Applicant: International Business Machines Corporation
Inventor： Richard H. Boivie , Eduard A. Cartier , Daniel J. Friedman , Kohji Hosokawa , Charanjit Jutla , Wanki Kim , Chandrasekara Kothandaraman , Chung Lam , Frank R. Libsch , Seiji Munetoh , Ramachandran Muralidhar , Vijay Narayanan , Dirk Pfeiffer , Devendra K. Sadana , Ghavam G. Shahidi , Robert L. Wisnieff
Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
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Patent Agency Ranking
公开(公告)号：US20180205017A1
公开(公告)日：2018-07-19
申请号：US15408392
申请日：2017-01-17
Applicant: International Business Machines Corporation
Inventor： Robert L. Bruce , Fabio Carta , Wanki Kim , Chung H. Lam
CPC classification number: H01L45/1683 , H01L27/2409 , H01L27/2427 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144
Abstract: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.
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公开(公告)号：US11715517B2
公开(公告)日：2023-08-01
申请号：US17396623
申请日：2021-08-06
Applicant: International Business Machines Corporation
Inventor： Ning Li , Wanki Kim , Devendra K Sadana
CPC classification number: G11C13/0004 , G06N3/063 , G11C13/004 , G11C13/0028
Abstract: A phase change (PCM) memory device that includes a PCM and a resistance-capacitance (RC) circuit. The PCM has one or more PCM properties, each PCM property has a plurality of PCM property states. As the PCM property states of a given property are Set or Reset, the PCM property states each produce an incremental change to a property level of the respective/associated PCM property, e.g., PCM conductance. The incremental changes to property level of the PCM memory device are in response to application of one or more of a pulse number of voltage pulses. The RC circuit produces a configuring current that flows through the PCM in response to one or more of the voltage pulses. The configuring current modifies one or more of the incremental changes to one or more of the property levels so that the property level changes lineally with respect to the pulse number. The PCM memory device has use in a synapse connector, e.g., in a memory array. The memory array can be used to store and/or read memory values associated with one or more of the property levels. The memory values can be used as weighting values in a neuromorphic computing application/system, like a neural network.
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公开(公告)号：US20230189670A1
公开(公告)日：2023-06-15
申请号：US17546178
申请日：2021-12-09
Applicant: International Business Machines Corporation
Inventor： Fabio Carta , Chung Hon Lam , Wanki Kim , Robert L. Bruce
CPC classification number: H01L45/1253 , H01L27/2436 , H01L45/06 , H01L45/144 , H01L45/1608
Abstract: A memory cell with a recessed bottom electrode and methods of forming the memory cell are described. A bottom electrode can be deposited on a layer of a structure. A first insulator and a second insulator can be deposited on top of the bottom electrode. The first insulator and the second insulator can be spaced apart from one another to form an opening on top of the bottom electrode. A recess can be etched in the bottom electrode. The recess can be etched in a portion of the bottom electrode that is underneath the opening. The recess and the opening can form a pore. Phase change material can be deposited in the pore to form a memory cell.
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公开(公告)号：US20230123642A1
公开(公告)日：2023-04-20
申请号：US18082189
申请日：2022-12-15
Applicant: International Business Machines Corporation
Inventor： Ning Li , Wanki Kim , Devendra K. Sadana
IPC: H10N70/00
Abstract: A phase change memory (PCM) structure configured for performing a gradual reset operation includes first and second electrodes and a phase change material layer disposed between the first and second electrodes. The PCM structure further includes a thermal insulation layer disposed on at least sidewalls of the first and second electrodes and phase change material layer. The thermal insulation layer is configured to provide non-uniform heating of the phase change material layer. Optionally, the thermal insulation layer may be formed as an air gap. The PCM structure may be configured having the first and second electrodes aligned in a vertical or a lateral arrangement.
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公开(公告)号：US20230044919A1
公开(公告)日：2023-02-09
申请号：US17396623
申请日：2021-08-06
Applicant: International Business Machines Corporation
Inventor： Ning Li , Wanki Kim , Devendra K. Sadana
Abstract: A phase change (PCM) memory device that includes a PCM and a resistance-capacitance (RC) circuit. The PCM has one or more PCM properties, each PCM property has a plurality of PCM property states. As the PCM property states of a given property are Set or Reset, the PCM property states each produce an incremental change to a property level of the respective/associated PCM property, e.g., PCM conductance. The incremental changes to property level of the PCM memory device are in response to application of one or more of a pulse number of voltage pulses. The RC circuit produces a configuring current that flows through the PCM in response to one or more of the voltage pulses. The configuring current modifies one or more of the incremental changes to one or more of the property levels so that the property level changes lineally with respect to the pulse number. The PCM memory device has use in a synapse connector, e.g., in a memory array. The memory array can be used to store and/or read memory values associated with one or more of the property levels. The memory values can be used as weighting values in a neuromorphic computing application/system, like a neural network.
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