公开(公告)号：US20230267094A1

公开(公告)日：2023-08-24

申请号：US17679330

申请日：2022-02-24

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Patrik Eder ,  Kajetan Nuernberger

IPC: G06F15/78 ,  G06F9/455 ,  G06F9/30

CPC classification number: G06F15/7807 ,  G06F9/45558 ,  G06F9/30003 ,  G06F2009/45591

Abstract: In various examples, a system on a chip is provided that is configured to be operated in a debug mode. The system on a chip includes a plurality of processor cores including a plurality of virtual machines and a further processor core, configured to, in the debug mode, initially execute first debug instructions after the system on a chip has started operating. The first debug instructions are configured to cause the further processor core to make a debug setting that, after the first debug instructions are executed, prevents a processor core executing second debug instructions from accessing at least one of the virtual machines and allows the processor core executing the second debug instructions to access at least one other of the virtual machines.

公开(公告)号：US20220309169A1

公开(公告)日：2022-09-29

申请号：US17700643

申请日：2022-03-22

Applicant: Infineon Technologies AG

Inventor： Joerg Syassen ,  Avni Bildhaiya ,  Andreas Graefe ,  Albrecht Mayer ,  Manuela Meier ,  Viola Rieger

IPC: G06F21/60 ,  G06F21/70

Abstract: A device includes a safety domain having a processing unit and a memory and is configured to provide at least one functionality and to implement one more safety measures for detecting faults. The safety domain is configured to transmit at least one alarm signal indicating one or more detected errors in response to detecting the faults. The device further includes a security domain having a processing unit and a memory and is configured to provide cryptographic services and to obtain alarm signals. The security domain is configured to perform security-related operations in a secure state in response to obtaining an alarm signal from the safety domain.

公开(公告)号：US20210367366A1

公开(公告)日：2021-11-25

申请号：US17329559

申请日：2021-05-25

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Patrik Eder

IPC: H01R12/75 ,  H01R13/66 ,  H01R13/04

Abstract: A circuitry is disclosed having one or more circuits and a connector portion coupled that is to the one or more circuits. The connector portion includes a plurality of pins, at least some of the pins having assigned functionality, and wherein at least one first pin is to activate a mechanism to bring the one or more circuits into an electrically safe state. The circuitry is configured, in case the connector portion is coupled with a first connector in a first orientation, to allow the one or more circuits to operate properly via the connector portion. The circuitry is also configured so that in a case where the connector portion is coupled with a second connector in a second orientation different from the first orientation, the at least one first pin of the plurality of pins receives a reference potential that triggers activation of a safety mechanism.

公开(公告)号：US10996956B2

公开(公告)日：2021-05-04

申请号：US15945114

申请日：2018-04-04

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Glenn Ashley Farrall

IPC: G06F9/38 ,  G06F9/30 ,  G06F11/34 ,  G06F11/30 ,  G05B19/042

Abstract: A method includes incrementing a counter with transmission of a process data from a first processor to a second processor, periodically decrementing the counter, if the counter is greater than a predetermined floor threshold value, wherein a period is a predetermined time interval; and stalling the first processor, if the counter is above a configurable load threshold value, so as to re-schedule the transmission of the process data from the first processor to the second processor.

公开(公告)号：US10782884B2

公开(公告)日：2020-09-22

申请号：US15588973

申请日：2017-05-08

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06

Abstract: A method of determining an access address includes determining a first address translation rule to translate a first input address to a first output address, determining a second address translation rule to translate a second input address to a second output address, and using at least one of the first address translation rule and the second address translation rule to determine the access address. An apparatus for accessing a memory based on a memory address includes a first address translator configured to translate a first input address to a first output address and a second address translator configured to translate a second input address to a second output address. The apparatus is configured to use at least one of the first address translator and the second address translator to translate the memory address to the access address.

公开(公告)号：US20180210852A1

公开(公告)日：2018-07-26

申请号：US15924934

申请日：2018-03-19

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Joerg Schepers ,  Frank Hellwig

IPC: G06F13/364 ,  G06F13/40 ,  G06F13/42 ,  G06F15/78 ,  G06F13/24

CPC classification number: G06F13/364 ,  G06F13/24 ,  G06F13/404 ,  G06F13/4282 ,  G06F15/7807

Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.

公开(公告)号：US20180052626A1

公开(公告)日：2018-02-22

申请号：US15670436

申请日：2017-08-07

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel ,  Albrecht Mayer

IPC: G06F3/06 ,  G06F11/07 ,  G06F11/10 ,  G11C11/56

CPC classification number: G06F3/0619 ,  G06F11/073 ,  G06F11/076 ,  G06F11/079 ,  G06F11/1072 ,  G11C11/5628

Abstract: The disclosure proposes a circuit including a memory which has a multiplicity of memory cells, the memory having a first area and a second area, at least one memory cell comprising a part of the first area and a part of the second area, the first area having a lower reliability than the second area, and the circuit being set up in such a manner that first bits are stored in the first area and second bits are stored in the second area. A circuit for reading the memory and methods for writing to and reading the memory are also disclosed.

公开(公告)号：US09792199B2

公开(公告)日：2017-10-17

申请号：US13689826

申请日：2012-11-30

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer

IPC: G06F11/34 ,  G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3466 ,  G06F11/3476 ,  G06F2201/865

Abstract: An automotive electronics system includes an electronic control unit and a trace adapter. The electronic control unit is configured to receive measurement signals and provide control signals. Additionally, the electronic control unit is configured to generate or provide trace signals by replacing original instructions in a binary image with trace instructions. The trace instructions are functionally equivalent, but trigger providing the trace signals. The trace adapter is coupled to the electronic control unit. The trace adapter is configured to obtain the trace signals from the electronic control unit.

公开(公告)号：US09740837B2

公开(公告)日：2017-08-22

申请号：US14453116

申请日：2014-08-06

Applicant: Infineon Technologies AG

Inventor： Witold Gora ,  Andreas Geiler ,  Gerd Dirscherl ,  Albrecht Mayer

IPC: G06F21/00 ,  G06F21/12 ,  G06F21/14 ,  G06F21/60

CPC classification number: G06F21/12 ,  G06F21/14 ,  G06F21/602 ,  G06F2221/0744

Abstract: An apparatus and corresponding method for preventing cloning of code. The apparatus includes a memory, an authentication module, and a device. The memory is configured to store the code, which includes unencrypted code and a fragment of encrypted code. The authentication module is configured to receive and decrypt the fragment of encrypted code from the memory into a fragment of decrypted code, and to store the fragment of decrypted code in an authentication module buffer. The device configured to execute the unencrypted code from the memory and to execute the fragment of decrypted code from the authentication module buffer, wherein the fragment of encrypted code is personalized to the device.

公开(公告)号：US20140239987A1

公开(公告)日：2014-08-28

申请号：US13777132

申请日：2013-02-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Albrecht Mayer ,  Simon Brewerton

IPC: G01R31/28

CPC classification number: G01R31/2894 ,  G01R31/3177

Abstract: A system and method for determining operational robustness of a system on a chip (SoC) includes modifying one or more internal states of the SoC, during operation of the SoC, to mimic an effect which one or more disturbances have on the SoC, generating one or more signal traces that correspond to at least one internal state of the SoC after modifying the one or more internal states of the SoC, and determining if the operation of the SoC is stable based on the one or more generated signal traces.

Abstract translation: 一种用于确定芯片上的系统（SoC）的操作鲁棒性的系统和方法包括：在SoC的操作期间修改SoC的一个或多个内部状态，以模拟一个或多个干扰对SoC的影响，产生一个 或更多的信号迹线，其在修改SoC的一个或多个内部状态之后对应于SoC的至少一个内部状态，以及基于所述一个或多个生成的信号迹线来确定SoC的操作是否稳定。