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公开(公告)号:US09691687B2
公开(公告)日:2017-06-27
申请号:US14266348
申请日:2014-04-30
Applicant: Infineon Technologies AG
Inventor: Daniel Kehrer , Ulrich Krumbein , Beng-Keh See , Horst Theuss , Helmut Wietschorke , Tze Yang Hin , Stefan Martens
CPC classification number: H01L23/495 , H01L23/3107 , H01L23/315 , H01L23/49548 , H01L23/49575 , H01L23/66 , H01L24/45 , H01L24/48 , H01L24/83 , H01L25/16 , H01L2223/6611 , H01L2224/16145 , H01L2224/16245 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/83 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01047 , H01L2924/01322 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
Abstract: A module and a method for manufacturing a module are disclosed. An embodiment of a module includes a first semiconductor device, a frame arranged on the first semiconductor device, the frame including a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.
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公开(公告)号:US09608305B2
公开(公告)日:2017-03-28
申请号:US14155130
申请日:2014-01-14
Applicant: Infineon Technologies AG
Inventor: Valentyn Solomko , Winfried Bakalski , Nikolay Ilkov , Werner Simbuerger , Daniel Kehrer
CPC classification number: H01P5/18 , G01R1/203 , G01R1/206 , G01R19/00 , G01R21/07 , H01P5/04 , H03H7/48
Abstract: A circuit includes a current sensing circuit comprising a current input terminal coupled to an input port, a current output terminal coupled to a transmitted port, and a current sensing output terminal configured to provide a current sensing signal proportional to a current flowing between the current input terminal and the current output terminal. The circuit further includes a voltage sensing circuit having a voltage input terminal coupled to the transmitted port and a voltage sensing output terminal configured to provide a voltage sensing signal proportional to a voltage at the transmitted port. A combining circuit has a first input coupled to the current sensing output terminal, a second input coupled to the voltage sensing output terminal, and a combined output node coupled to an output port.
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公开(公告)号:US20160359504A1
公开(公告)日:2016-12-08
申请号:US15241736
申请日:2016-08-19
Applicant: Infineon Technologies AG
Inventor: Daniel Kehrer
CPC classification number: H04B1/006 , H04B1/1027 , H04B7/0452
Abstract: According to an embodiment, a circuit package includes a programmable switch component having a plurality of input terminals arranged on the programmable switch component, a plurality of output terminals arranged on the programmable switch component and configured to be coupled to a plurality of amplifiers, and a plurality of switches. Each switch of the plurality of switches is coupled between an input terminal of the plurality of input terminals and an output terminal of the plurality of output terminals. Each switch of the plurality of switches includes a radio frequency (RF) switch and is configured to pass an RF signal when closed. Each input terminal of the plurality of input terminals is coupled to two switches of the plurality of switches.
Abstract translation: 根据实施例,电路封装包括具有布置在可编程开关组件上的多个输入端的可编程开关组件,布置在可编程开关组件上并被配置为耦合到多个放大器的多个输出端子,以及 多个开关。 多个开关的每个开关耦合在多个输入端子的输入端子和多个输出端子的输出端子之间。 多个开关的每个开关包括射频(RF)开关,并且被配置为在关闭时传递RF信号。 多个输入端子的每个输入端子耦合到多个开关的两个开关。
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公开(公告)号:US09337775B1
公开(公告)日:2016-05-10
申请号:US14561789
申请日:2014-12-05
Applicant: Infineon Technologies AG
Inventor: Nikolay Ilkov , Paulo Oliveira , Daniel Kehrer
CPC classification number: H03F3/19 , H03F1/0261 , H03F3/191 , H03F2200/111 , H03F2200/249 , H03F2200/294 , H03F2200/39 , H03F2200/451 , H04B1/10
Abstract: In accordance with an embodiment, a circuit includes a low noise amplifier transistor disposed on a first integrated circuit, a single pole multi throw (SPMT) switch disposed on a second integrated circuit, and a bypass switch coupled between a control node of the low noise amplifier transistor and an output node of the low noise amplifier transistor. The SPMT switch couples a plurality of module input terminals to a control node of the low noise amplifier transistor, and the bypass switch including a first switch coupled between the control node of the low noise amplifier transistor and an intermediate node, a second switch coupled between the intermediate node and the output node of the low noise amplifier transistor, and a third switch coupled between the intermediate node and a first reference node. The first integrated circuit and the second integrated circuit are disposed on a substrate.
Abstract translation: 根据实施例,电路包括设置在第一集成电路上的低噪声放大器晶体管,设置在第二集成电路上的单极多掷(SPMT)开关,以及耦合在低噪声控制节点之间的旁路开关 放大器晶体管和低噪声放大器晶体管的输出节点。 SPMT开关将多个模块输入端子耦合到低噪声放大器晶体管的控制节点,并且旁路开关包括耦合在低噪声放大器晶体管的控制节点和中间节点之间的第一开关,第二开关耦合在 低噪声放大器晶体管的中间节点和输出节点,以及耦合在中间节点和第一参考节点之间的第三开关。 第一集成电路和第二集成电路设置在基板上。
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公开(公告)号:US20160056774A1
公开(公告)日:2016-02-25
申请号:US14462793
申请日:2014-08-19
Applicant: Infineon Technologies AG
Inventor: Nikolay Ilkov , Paulo Oliveira , Winfried Bakalski , Daniel Kehrer
CPC classification number: H03F1/565 , H03F1/0205 , H03F3/19 , H03F2200/213 , H03F2200/222 , H03F2200/252 , H03F2200/294 , H03F2200/421 , H03F2200/451
Abstract: In accordance with an embodiment, a circuit includes a first signal path coupled between an input port and an output port, and a second coupled between the input port and the output port in parallel with the first signal path. The first signal path includes a low noise amplifier (LNA) having an input node coupled to the input port, and the second signal path includes a switch coupled between the input port and the output port.
Abstract translation: 根据实施例,电路包括耦合在输入端口和输出端口之间的第一信号路径,以及耦合在输入端口和输出端口之间并与第一信号路径连接的第二信号路径。 第一信号路径包括具有耦合到输入端口的输入节点的低噪声放大器(LNA),并且第二信号路径包括耦合在输入端口和输出端口之间的开关。
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公开(公告)号:US20140332936A1
公开(公告)日:2014-11-13
申请号:US13889370
申请日:2013-05-08
Applicant: INFINEON TECHNOLOGIES AG
Inventor: Gottfried Beer , Dominic Maier , Ulrich Wachter , Daniel Kehrer
IPC: H01L23/552 , H01L21/56
CPC classification number: H01L23/552 , H01L21/56 , H01L23/3121 , H01L23/3128 , H01L24/18 , H01L24/19 , H01L24/20 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/181 , H01L2924/00
Abstract: In various embodiments, a package arrangement may be provided. The package arrangement may include at least one chip. The package arrangement may further include encapsulation material at least partially encapsulating the chip. The package arrangement may also include a redistribution structure over a first side of the chip. The package arrangement may further include a metal structure over a second side of the chip. The second side may be opposite the first side. The package arrangement may additionally include at least one of a semiconductor structure and an electrically conductive plastic material structure electrically coupled to the redistribution structure and the metal structure to form a current path between the redistribution structure and the metal structure.
Abstract translation: 在各种实施例中,可以提供包装布置。 封装结构可以包括至少一个芯片。 封装结构还可以包括至少部分地封装芯片的封装材料。 封装布置还可以包括在芯片的第一侧上的再分布结构。 封装布置还可以包括在芯片的第二侧上的金属结构。 第二面可以与第一面相对。 封装结构可以另外包括半导体结构和导电塑料材料结构中的至少一个,该结构电耦合到再分布结构和金属结构,以形成再分布结构和金属结构之间的电流路径。
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公开(公告)号:US09886407B2
公开(公告)日:2018-02-06
申请号:US14213173
申请日:2014-03-14
Applicant: Infineon Technologies AG
Inventor: Daniel Kehrer
CPC classification number: G06F13/4022 , H04B1/005
Abstract: In accordance with an embodiment of the present invention, a chip set for a mobile device includes a slave device chip and an interface circuit chip that includes a slave bus interface for controlling the slave device chip through an analog bus. The slave bus interface is coupled to a master bus interface via a digital bus of the mobile device. The slave bus interface is configured to be driven by the master bus interface.
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公开(公告)号:US09490852B2
公开(公告)日:2016-11-08
申请号:US14252322
申请日:2014-04-14
Applicant: Infineon Technologies AG
Inventor: Daniel Kehrer
CPC classification number: H04B1/006 , H04B1/1027 , H04B7/0452
Abstract: According to an embodiment, a circuit package includes a programmable switch component having a plurality of input terminals arranged on the programmable switch component, a plurality of output terminals arranged on the programmable switch component and configured to be coupled to a plurality of amplifiers, and a plurality of switches. Each switch of the plurality of switches is coupled between an input terminal of the plurality of input terminals and an output terminal of the plurality of output terminals. Each switch of the plurality of switches includes a radio frequency (RF) switch and is configured to pass an RF signal when closed. Each input terminal of the plurality of input terminals is coupled to two switches of the plurality of switches.
Abstract translation: 根据实施例,电路封装包括具有布置在可编程开关组件上的多个输入端的可编程开关组件,布置在可编程开关组件上并被配置为耦合到多个放大器的多个输出端子,以及 多个开关。 多个开关的每个开关耦合在多个输入端子的输入端子和多个输出端子的输出端子之间。 多个开关的每个开关包括射频(RF)开关,并且被配置为在关闭时传递RF信号。 多个输入端子的每个输入端子耦合到多个开关的两个开关。
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公开(公告)号:US20160233836A1
公开(公告)日:2016-08-11
申请号:US15130488
申请日:2016-04-15
Applicant: Infineon Technologies AG
Inventor: Daniel Kehrer , Paulo Oliveira , Thomas Leitner
CPC classification number: H03F1/26 , H03F1/565 , H03F3/19 , H03F3/193 , H03F3/211 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/391 , H03F2200/451 , H03F2203/21109 , H03F2203/21112 , H03F2203/21136 , H04B1/006 , H04B1/10 , H04B1/18
Abstract: An embodiment described herein includes a low noise amplifier (LNA) including a plurality of separate input terminals, a plurality of transistors, and an output network coupled to a first reference terminal and a single output of the LNA. Each transistor includes a conduction path and a control terminal coupled to one of the plurality of separate input terminals. The output network is also coupled to the conduction path of each of the plurality of transistors.
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公开(公告)号:US09374042B2
公开(公告)日:2016-06-21
申请号:US14227479
申请日:2014-03-27
Applicant: Infineon Technologies AG
Inventor: Daniel Kehrer , Paulo Oliveira , Thomas Leitner
CPC classification number: H03F1/26 , H03F1/565 , H03F3/19 , H03F3/193 , H03F3/211 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/391 , H03F2200/451 , H03F2203/21109 , H03F2203/21112 , H03F2203/21136 , H04B1/006 , H04B1/10 , H04B1/18
Abstract: An embodiment described herein includes a low noise amplifier (LNA) including a plurality of separate input terminals, a plurality of transistors, and an output network coupled to a first reference terminal and a single output of the LNA. Each transistor includes a conduction path and a control terminal coupled to one of the plurality of separate input terminals. The output network is also coupled to the conduction path of each of the plurality of transistors.
Abstract translation: 本文描述的实施例包括包括多个单独的输入端子,多个晶体管的低噪声放大器(LNA)以及耦合到第一参考端子和LNA的单个输出端的输出网络。 每个晶体管包括耦合到所述多个分离的输入端之一的导通路径和控制端。 输出网络也耦合到多个晶体管中的每一个的导通路径。
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