公开(公告)号：US09620457B2

公开(公告)日：2017-04-11

申请号：US14090570

申请日：2013-11-26

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Eva Wagner ,  Gottfried Beer

IPC: H01L23/544 ,  H01L21/78 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  B23K26/40 ,  B23K26/402 ,  B23K26/364 ,  B23K103/08 ,  B23K103/16 ,  B23K103/00 ,  B23K103/10 ,  B23K103/12 ,  B23K103/14 ,  B23K103/18

CPC classification number: H01L23/544 ,  B23K26/364 ,  B23K26/40 ,  B23K26/402 ,  B23K2103/08 ,  B23K2103/10 ,  B23K2103/12 ,  B23K2103/14 ,  B23K2103/172 ,  B23K2103/26 ,  B23K2103/30 ,  B23K2103/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device package includes encapsulating at least partially a plurality of semiconductor chips with encapsulating material to form an encapsulation body. The encapsulation body has a first main surface and a second main surface. At least one of a metal layer and an organic layer is formed over the first main surface of the encapsulation body. At least one trace of the at least one of the metal layer and the organic layer is removed by laser ablation. The encapsulation body is then separated into a plurality of semiconductor device packages along the at least one trace.

公开(公告)号：US20160090294A1

公开(公告)日：2016-03-31

申请号：US14495920

申请日：2014-09-25

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Thomas Kilger

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81C1/00238 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/81

Abstract: According to various embodiments, a package arrangement may include: a first encapsulation material; at least one electronic circuit at least partially embedded in the first encapsulation material, the at least one electronic circuit including a first contact pad structure at a first side of the at least one electronic circuit; at least one electromechanical device disposed over the first side of the at least one electronic circuit, the at least one electromechanical device including a second contact pad structure facing the first side of the at least one electronic circuit; a redistribution layer structure between the at least one electromechanical device and the at least one electronic circuit, the redistribution layer structure electrically connecting the first contact pad structure with the second contact pad structure, wherein a gap is provided between the at least one electromechanical device and the redistribution layer structure; a second encapsulation material at least partially covering the at least one electromechanical device, wherein the gap is free of the second encapsulation material.

Abstract translation: 根据各种实施例，封装结构可以包括：第一封装材料; 至少一个电子电路至少部分地嵌入在所述第一封装材料中，所述至少一个电子电路包括在所述至少一个电子电路的第一侧的第一接触焊盘结构; 设置在所述至少一个电子电路的第一侧上的至少一个机电装置，所述至少一个机电装置包括面向所述至少一个电子电路的第一侧的第二接触垫结构; 所述再分配层结构在所述至少一个机电装置和所述至少一个电子电路之间，所述再分配层结构将所述第一接触焊盘结构与所述第二接触焊盘结构电连接，其中，在所述至少一个机电装置和 再分配层结构; 至少部分地覆盖所述至少一个机电装置的第二封装材料，其中所述间隙不含所述第二封装材料。

公开(公告)号：US08890284B2

公开(公告)日：2014-11-18

申请号：US13774541

申请日：2013-02-22

Applicant: Infineon Technologies AG

Inventor： Thomas Kilger ,  Ulrich Wachter ,  Dominic Maier ,  Gottfried Beer

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/538 ,  H01L21/82 ,  H01L27/04

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L21/82 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/50 ,  H01L27/04 ,  H01L28/00 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/00

Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.

Abstract translation: 多个半导体芯片各自包括与第一主面相对的第一主面和第二主面。 在半导体芯片的第二主面上施加第一封装层。 在第一半导体芯片的第一主面上施加电布线层。 将第二封装层施加在电布线层上。 第一封装层的厚度和第一半导体芯片的厚度减小。 可以将该结构单个化以获得多个半导体器件。

公开(公告)号：US09275878B2

公开(公告)日：2016-03-01

申请号：US14043138

申请日：2013-10-01

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Dominic Maier ,  Thomas Kilger

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76838 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/48 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02317 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.

Abstract translation: 集成电路通过将多个半导体管芯放置在支撑衬底上而被封装，每个半导体管芯在面向支撑衬底的一侧具有多个端子，并用模制化合物覆盖半导体管芯以形成模制结构。 然后将支撑基板从模制结构中取出，以使端子露出半导体管芯的一侧，并且在模制结构上形成金属再分布层，并与半导体管芯和模塑料的端子直接接触。 形成再分配层，而不用半导体管芯的端子在模制结构的一侧形成电介质层。 还公开了相应的模制基板和单独的模制半导体封装。

公开(公告)号：US20160035677A1

公开(公告)日：2016-02-04

申请号：US14450307

申请日：2014-08-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ulrich Wachter ,  Thomas Kilger

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/552 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3157 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A method for forming a package arrangement is provided, which may include: arranging at least one chip over a carrier; at least partially encapsulating the at least one chip with encapsulation material, wherein the encapsulation material is formed such that at least a portion of the carrier is uncovered by the encapsulation material; forming an electrically conductive structure over the encapsulation material and on the portion of the carrier uncovered by the encapsulation material; removing the carrier; and then forming a redistribution structure over the chip and the electrically conductive structure, wherein the redistribution structure electrically couples the electrically conductive structure and the chip.

Abstract translation: 提供了一种用于形成封装结构的方法，其可以包括：在载体上布置至少一个芯片; 至少部分地用封装材料封装所述至少一个芯片，其中所述封装材料形成为使得所述载体的至少一部分未被所述封装材料覆盖; 在所述封装材料和所述载体的由所述封装材料覆盖的部分上形成导电结构; 移除载体; 然后在所述芯片和所述导电结构上形成再分布结构，其中所述再分布结构电耦合所述导电结构和所述芯片。

公开(公告)号：US09147585B2

公开(公告)日：2015-09-29

申请号：US14535591

申请日：2014-11-07

Applicant: Infineon Technologies AG

Inventor： Thomas Kilger ,  Ulrich Wachter ,  Dominic Maier ,  Gottfried Beer

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/82 ,  H01L21/56 ,  H01L23/538 ,  H01L27/04 ,  H01L49/02 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L21/82 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/50 ,  H01L27/04 ,  H01L28/00 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/00

Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.

Abstract translation: 多个半导体芯片各自包括与第一主面相对的第一主面和第二主面。 在半导体芯片的第二主面上施加第一封装层。 在第一半导体芯片的第一主面上施加电布线层。 将第二封装层施加在电布线层上。 第一封装层的厚度和第一半导体芯片的厚度减小。 可以将该结构单个化以获得多个半导体器件。

公开(公告)号：US09099454B2

公开(公告)日：2015-08-04

申请号：US13964153

申请日：2013-08-12

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Veronika Huber ,  Thomas Kilger ,  Ralf Otremba ,  Bernd Stadler ,  Dominic Maier ,  Klaus Schiess ,  Andreas Schlögl ,  Uwe Wahl

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/36 ,  H01L21/56

CPC classification number: H01L23/49575 ,  H01L21/561 ,  H01L21/568 ,  H01L23/36 ,  H01L23/49562 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/96 ,  H01L27/14618 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/73273 ,  H01L2224/73277 ,  H01L2224/85 ,  H01L2224/96 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00014

Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.

Abstract translation: 通过在模具的第一侧提供具有端子的半导体模具来制造半导体封装，在模具的相对的第二侧提供耦合到模具的材料，并将模具嵌入模制化合物中，使得模具被覆盖 通过除第一面以外的所有侧面的模塑料。 模塑料在靠近模具的第二侧的模塑料的一侧变细，以在模具的第二面露出材料，而不暴露模具的第二面。 在模具的第一侧上的端子形成电连接。 在晶体管管芯的情况下，端子可以是源极端子，并且晶体管管芯可以源极地附接到诸如引线框架的管芯焊盘的金属块。

公开(公告)号：US20150041967A1

公开(公告)日：2015-02-12

申请号：US13964153

申请日：2013-08-12

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Veronika Huber ,  Thomas Kilger ,  Ralf Otremba ,  Bernd Stadler ,  Dominic Maier ,  Klaus Schiess ,  Andreas Schlögl ,  Uwe Wahl

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/561 ,  H01L21/568 ,  H01L23/36 ,  H01L23/49562 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/96 ,  H01L27/14618 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/73273 ,  H01L2224/73277 ,  H01L2224/85 ,  H01L2224/96 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00014

Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.

Abstract translation: 通过在模具的第一侧提供具有端子的半导体模具来制造半导体封装，在模具的相对的第二侧提供耦合到模具的材料，并将模具嵌入模制化合物中，使得模具被覆盖 通过除第一面以外的所有侧面的模塑料。 模塑料在靠近模具的第二侧的模塑料的一侧变细，以在模具的第二面露出材料，而不暴露模具的第二面。 在模具的第一侧上的端子形成电连接。 在晶体管管芯的情况下，端子可以是源极端子，并且晶体管管芯可以源极地附接到诸如引线框架的管芯焊盘的金属块。

公开(公告)号：US09718678B2

公开(公告)日：2017-08-01

申请号：US14495920

申请日：2014-09-25

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Thomas Kilger

IPC: H01L23/02 ,  B81C1/00

CPC classification number: B81C1/00238 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/81

Abstract: According to various embodiments, a package arrangement may include: a first encapsulation material; at least one electronic circuit at least partially embedded in the first encapsulation material, the at least one electronic circuit including a first contact pad structure at a first side of the at least one electronic circuit; at least one electromechanical device disposed over the first side of the at least one electronic circuit, the at least one electromechanical device including a second contact pad structure facing the first side of the at least one electronic circuit; a redistribution layer structure between the at least one electromechanical device and the at least one electronic circuit, the redistribution layer structure electrically connecting the first contact pad structure with the second contact pad structure, wherein a gap is provided between the at least one electromechanical device and the redistribution layer structure; a second encapsulation material at least partially covering the at least one electromechanical device, wherein the gap is free of the second encapsulation material.

公开(公告)号：US09487392B2

公开(公告)日：2016-11-08

申请号：US14454247

申请日：2014-08-07

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Dominic Maier ,  Thomas Kilger

IPC: B81C1/00 ,  H01L23/48 ,  H01L23/00 ,  H01L23/552 ,  B81B7/00 ,  H01L21/56 ,  H03H9/10 ,  H04R19/00

CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B2201/0257 ,  H01L21/568 ,  H01L23/48 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H03H9/1064 ,  H04R19/005 ,  H01L2924/00

Abstract: A method of packaging integrated circuits includes providing a molded substrate that has a plurality of first semiconductor dies and a plurality of second semiconductor dies laterally spaced apart from one another and covered by a molding compound. The molding compound is thinned to expose at least some of the second semiconductor dies. The exposed second semiconductor dies are removed to form cavities in the molded substrate. A plurality of third semiconductor dies are inserted in the cavities formed in the molded substrate, and electrical connections are formed to the first semiconductor dies and to the third semiconductor dies.

Abstract translation: 一种封装集成电路的方法包括：提供具有多个第一半导体管芯和多个第二半导体管芯的模制衬底，所述第二半导体管芯相互间隔开并被模制化合物覆盖。 将模塑料稀薄以暴露至少一些第二半导体管芯。 暴露的第二半导体管芯被移除以在模塑衬底中形成空腔。 多个第三半导体管芯被插入形成在模制基板中的空腔中，并且电连接形成于第一半导体管芯和第三半导体管芯。