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    Fault check without software intervention
    11.
    发明授权
    Fault check without software intervention 有权

    公开(公告)号：US11526389B2

    公开(公告)日：2022-12-13

    申请号：US16891312

    申请日：2020-06-03

    Applicant: Infineon Technologies AG

    Inventor： Ketan Dewan ,  Juergen Schaefer

    IPC: G05B23/02 ,  G06F11/07 ,  G08B21/18 ,  B60W50/02 ,  H04L12/40 ,  B60W50/00

    Abstract: A fault check circuit, including a first channel comparator to output a first channel comparator output signal indicating whether a first channel digital signal is outside of a first channel threshold range, wherein the first channel digital signal is A/D converted from a first channel analog signal; a second channel comparator to output a second channel comparator output signal indicating whether a second channel digital signal is outside of a second channel threshold range, wherein the second channel digital signal is A/D converted from a second channel analog signal; and an alarm generator circuit to combine the first and second channel comparator output signals, and output a fault check signal, wherein the first and second channel comparators and the alarm generator circuit are implemented in hardware, and the fault check circuit performs a fault check without software intervention.

    IMPLEMENTATION TO DETECT FAILURE OR FAULT ON AN ANALOG INPUT PATH FOR SINGLE ANALOG INPUT FUNCTIONAL SAFETY APPLICATIONS
    13.
    发明申请
    IMPLEMENTATION TO DETECT FAILURE OR FAULT ON AN ANALOG INPUT PATH FOR SINGLE ANALOG INPUT FUNCTIONAL SAFETY APPLICATIONS 有权

    公开(公告)号：US20220276323A1

    公开(公告)日：2022-09-01

    申请号：US17739347

    申请日：2022-05-09

    Applicant: Infineon Technologies AG

    Inventor： Ketan Dewan ,  Rocco Calabro ,  Juergen Schaefer

    IPC: G01R31/54 ,  H03M1/12

    Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.

    Implementation to detect failure or fault on an analog input path for single analog input functional safety applications
    14.
    发明授权
    Implementation to detect failure or fault on an analog input path for single analog input functional safety applications 有权

    公开(公告)号：US11353517B1

    公开(公告)日：2022-06-07

    申请号：US17114915

    申请日：2020-12-08

    Applicant: Infineon Technologies AG

    Inventor： Ketan Dewan ,  Rocco Calabro ,  Juergen Schaefer

    IPC: G01R31/54 ,  H03M1/12

    Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.

    Pad asymmetry compensation
    15.
    发明授权
    Pad asymmetry compensation 有权

    公开(公告)号：US10305506B2

    公开(公告)日：2019-05-28

    申请号：US15690728

    申请日：2017-08-30

    Applicant: Infineon Technologies AG

    Inventor： Ketan Dewan ,  Reinhard Kussian ,  Juergen Schaefer

    IPC: H03M3/00

    Abstract: A modulator including a delta-sigma modulation circuit having an order greater than 1, and configured to modulate an input signal into a Pulse Density Modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit configured to linearize a relation between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal, and to output a modified PDM signal, wherein the linearized relation is for compensating for any offset in the PDM signal.

    IMPLEMENTATION TO DETECT FAILURE OR FAULT ON AN ANALOG INPUT PATH FOR SINGLE ANALOG INPUT FUNCTIONAL SAFETY APPLICATIONS
    18.
    发明申请
    IMPLEMENTATION TO DETECT FAILURE OR FAULT ON AN ANALOG INPUT PATH FOR SINGLE ANALOG INPUT FUNCTIONAL SAFETY APPLICATIONS 有权

    公开(公告)号：US20220179012A1

    公开(公告)日：2022-06-09

    申请号：US17114915

    申请日：2020-12-08

    Applicant: Infineon Technologies AG

    Inventor： Ketan Dewan ,  Rocco Calabro ,  Juergen Schaefer

    IPC: G01R31/54 ,  H03M1/12

    Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.

    TIME MEASUREMENT OF A CLOCK-BASED SIGNAL
    20.
    发明申请
    TIME MEASUREMENT OF A CLOCK-BASED SIGNAL 有权

    公开(公告)号：US20220085824A1

    公开(公告)日：2022-03-17

    申请号：US17467767

    申请日：2021-09-07

    Applicant: Infineon Technologies AG

    Inventor： Mihail Jefremow ,  Ketan Dewan ,  Rex Kho ,  Ralph Mueller-Eschenbach ,  Juergen Schaefer

    IPC: H03M1/12 ,  G06F1/10 ,  G01R31/317

    Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.

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