公开(公告)号：US20150303128A1

公开(公告)日：2015-10-22

申请号：US14254139

申请日：2014-04-16

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Oliver Haeberlen ,  Matteo-Alessandro Kutschak

IPC: H01L23/373 ,  H01L23/522 ,  H01L23/31 ,  H01L25/10 ,  H01L23/495

CPC classification number: H01L23/3157 ,  H01L21/4842 ,  H01L21/568 ,  H01L23/142 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/48 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/06181 ,  H01L2224/24175 ,  H01L2224/24246 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/40137 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/73263 ,  H01L2224/73267 ,  H01L2224/8382 ,  H01L2224/92244 ,  H01L2225/1029 ,  H01L2225/1047 ,  H01L2924/00 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/014

Abstract: A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact.

Abstract translation: 一种器件包括布置在第一载体上并包括第一电触点的第一半导体芯片。 该装置还包括布置在第二载体上的第二半导体芯片，并且包括布置在面向第二载体的第二半导体芯片的表面上的第二电触点。 第二载体电耦合到第一电接触和第二电接触。

公开(公告)号：US10418319B2

公开(公告)日：2019-09-17

申请号：US13893937

申请日：2013-05-14

Applicant: Infineon Technologies AG

Inventor： Oliver Haeberlen ,  Klaus Schiess ,  Stefan Kramp

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/14 ,  H01L23/36 ,  H01L23/492 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer.

公开(公告)号：US09224806B2

公开(公告)日：2015-12-29

申请号：US13961155

申请日：2013-08-07

Applicant: Infineon Technologies AG

Inventor： Stephan Voss ,  Alexander Breymesser ,  Hans-Joachim Schulze ,  Erich Griebl ,  Oliver Haeberlen ,  Andreas Moser

IPC: H01L29/06 ,  H01L21/761

CPC classification number: H01L29/063 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor body and an edge termination structure. The edge termination structure comprises a first oxide layer, a second oxide layer, a semiconductor mesa region between the first oxide layer and the second oxide layer, and a doped field region comprising a first section in the semiconductor mesa region, and a second section in a region below the semiconductor mesa region. The second section overlaps the first and the second oxide layers in the region below the semiconductor mesa region.

Abstract translation: 半导体器件包括半导体本体和边缘端接结构。 边缘终端结构包括第一氧化物层，第二氧化物层，第一氧化物层和第二氧化物层之间的半导体台面区域，以及包括半导体台面区域中的第一部分的掺杂场区域，以及第二部分 半导体台面区域以下的区域。 第二部分与半导体台面区域下方的区域中的第一和第二氧化物层重叠。