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公开(公告)号：US09152257B2
公开(公告)日：2015-10-06
申请号：US13730642
申请日：2012-12-28
Applicant: Intel Corporation
Inventor： James A. McCall , Kuljit S. Bains , Derek M. Conrow , Aaron Martin
IPC: H03K3/012 , G06F3/041 , H03K19/00 , H03K19/0175
CPC classification number: H03K19/0008 , G06F3/041 , G06F3/0412 , H03K19/0005 , H03K19/017509 , H03K19/017545
Abstract: An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low.
Abstract translation: 输出驱动器包括被配置为接通上拉电路和下拉电路以提供传输线路上的逻辑低电平的输出阻抗的控制逻辑。 输出驱动器包括一个可变上拉电阻。 控制逻辑被配置为将上拉电路接通到第一阻抗值，以驱动传输线上的逻辑高电平。 控制逻辑被配置为将上拉电路接通到第二阻抗值，并且接通下拉电路以提供输出阻抗以驱动传输线上的逻辑低电平。 可替代地，该系统可以被配置为用于将逻辑高的上拉电路和下拉电路的组合打开，其中下拉电路被接通为逻辑低电平。
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公开(公告)号：US20170243627A1
公开(公告)日：2017-08-24
申请号：US15047427
申请日：2016-02-18
Applicant: Intel Corporation
Inventor： Mozhgan Mansuri , Aaron Martin , James A. McCall
IPC: G11C11/4076 , H03K5/14
CPC classification number: G11C11/4076 , G06F1/10 , G06F13/4234 , G11C7/10 , G11C7/1087 , G11C7/222 , G11C11/4093 , H03K5/14 , H03K2005/00052 , H04L7/0337
Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.
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公开(公告)号：US09374004B2
公开(公告)日：2016-06-21
申请号：US13931604
申请日：2013-06-28
Applicant: Intel Corporation
Inventor： Christopher P. Mozak , Ritesh B. Trivedi , James A. McCall , Aaron Martin
IPC: H03K19/0175 , H03K19/0185 , H02M3/158 , G11C29/02 , G11C7/10 , H04L25/02
CPC classification number: H02M3/158 , G11C7/1057 , G11C29/022 , G11C29/025 , G11C29/028 , G11C2207/105 , H04L25/0276 , H04L25/029
Abstract: A transmission line interface circuit includes a voltage regulator to control a voltage swing of the transmission line interface circuit for signal transmission. The transmission line interface circuit includes complementary driver elements, including a p-type driver element to pull up the transmission line in response to a logic high, and an n-type driver element to pull down the transmission line in response to a logic low. The voltage regulator is coupled between one of the driver elements and a respective voltage reference to reduce a voltage swing of the transmission line interface circuit.
Abstract translation: 传输线接口电路包括用于控制用于信号传输的传输线接口电路的电压摆幅的电压调节器。 传输线接口电路包括互补驱动器元件，包括响应于逻辑高来上拉传输线的p型驱动器元件，以及响应于逻辑低来拉低传输线的n型驱动器元件。 电压调节器耦合在驱动器元件之一和相应的电压基准之间，以减小传输线接口电路的电压摆幅。
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Patent Agency Ranking
公开(公告)号：US20160087918A1
公开(公告)日：2016-03-24
申请号：US14494190
申请日：2014-09-23
Applicant: Intel Corporation
Inventor： Roger K. Cheng , Stefan Rusu , Aaron Martin
IPC: H04L12/931 , G06F17/50
CPC classification number: G06F17/5063 , G06F2217/78 , H03M1/12 , H03M1/66
Abstract: Described is an apparatus which comprises: logic to convert output of at least one sensor to a digital sensing signal; a router coupled to the sensor, the router to receive the digital sensing signal and to map into circuit data; and one or more communication interfaces, coupled to the router, to forward circuit data to a circuit endpoint. Described is a method which comprises: providing one or more digital sensing signals from a plurality of sensors; receiving the one or more digital sensing signals; generating packets of data using the one or more digital sensing signals; and providing the packets of data to one or more destinations.
Abstract translation: 描述了一种装置，其包括：将至少一个传感器的输出转换为数字感测信号的逻辑; 路由器耦合到传感器，路由器接收数字感测信号并映射到电路数据中; 以及耦合到路由器的一个或多个通信接口，以将电路数据转发到电路端点。 描述了一种方法，其包括：从多个传感器提供一个或多个数字感测信号; 接收一个或多个数字感测信号; 使用所述一个或多个数字感测信号产生数据包; 并将数据包提供给一个或多个目的地。
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15.发明授权公开(公告)号：US11722128B2
公开(公告)日：2023-08-08
申请号：US17357456
申请日：2021-06-24
Applicant: Intel Corporation
Inventor： Aaron Martin , Roger Cheng , Hari Venkatramani , Navneet Dour , Mozhgan Mansuri , Bryan Casper , Frank O'Mahony , Ganesh Balamurugan , Ajay Balankutty , Kuan Zhou , Sridhar Tirumalai , Krishnamurthy Venkataramana , Alex Thomas , Quoc Nguyen
CPC classification number: H03K5/1565 , G06F1/08 , G11C7/1057 , G11C7/1066 , G11C7/1084 , G11C7/1093 , G11C7/222 , H03L7/0812
Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
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公开(公告)号：US10672438B2
公开(公告)日：2020-06-02
申请号：US16147635
申请日：2018-09-29
Applicant: Intel Corporation
Inventor： Mohammed G. Mostofa , Roger K. Cheng , Aaron Martin , Christopher Mozak , Pavan Kumar Kappagantula , Hsien-Pao Yang
IPC: G11C7/10 , G06F1/3234 , G06F13/16
Abstract: An apparatus is provided which comprises: a first circuitry to sample a first input signal to generate a first sampled signal, and to sample a second input signal to generate a second sampled signal, wherein the first input signal comprises data; a second circuitry to receive the first sampled signal and the second sampled signal, and to generate a first pair of differential signals; an offset cancellation circuitry to cancel or reduce an offset in the first pair of differential signals; and a latch to receive the first pair of differential signals subsequent to the cancellation or reduction of the offset, and to output a second pair of differential signals, wherein the second pair of differential signals is indicative of the data.
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公开(公告)号：US10025333B2
公开(公告)日：2018-07-17
申请号：US14638928
申请日：2015-03-04
Applicant: Intel Corporation
Inventor： Moonkyun Maeng , Aaron Martin
Abstract: Described is an apparatus which comprises: a first feedback loop to generate a control signal for regulating an output voltage provided to a load; and a second feedback loop, separate from the first feedback loop, to receive the control signal from the first feedback loop, the second feedback loop to regulate the output voltage provided to the load.
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公开(公告)号：US10007749B2
公开(公告)日：2018-06-26
申请号：US14494190
申请日：2014-09-23
Applicant: Intel Corporation
Inventor： Roger K. Cheng , Stefan Rusu , Aaron Martin
CPC classification number: G06F17/5063 , G06F2217/78 , H03M1/12 , H03M1/66
Abstract: Described is an apparatus which comprises: logic to convert output of at least one sensor to a digital sensing signal; a router coupled to the sensor, the router to receive the digital sensing signal and to map into circuit data; and one or more communication interfaces, coupled to the router, to forward circuit data to a circuit endpoint. Described is a method which comprises: providing one or more digital sensing signals from a plurality of sensors; receiving the one or more digital sensing signals; generating packets of data using the one or more digital sensing signals; and providing the packets of data to one or more destinations.
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