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    Device, method and system to determine a mode of voltage regulation based on parasitics of a power delivery network
    11.
    发明授权
    Device, method and system to determine a mode of voltage regulation based on parasitics of a power delivery network 有权

    公开(公告)号：US12164322B2

    公开(公告)日：2024-12-10

    申请号：US17359413

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Amit K. Jain ,  Mauricio Aguilar Salas ,  Jonathan Douglas ,  Anant Deval

    IPC: G05F1/59 ,  G05F1/575 ,  G06F1/3203

    Abstract: Techniques and mechanisms for determining an operational mode of a voltage regulator. In an embodiment, an integrated circuit (IC) die is coupled to receive power from a voltage regulator (VR) via a power delivery network (PDN) which comprises circuitry in or on a substrate, such as that of a printed circuit board. The IC die receives from the substrate information indicating a characteristic of a parasitic impedance at the substrate. Based on the information, a controller unit at the IC die selects one of multiple VR modes which each correspond to a respective one of different parasitic impedance characteristics. The controller then signals the VR to provide the selected mode. In an embodiment one of the VR modes corresponds to a relatively high impedance, and also corresponds to a relatively stable sensitivity function in a frequency range above a control bandwidth.

    TECHNOLOGIES FOR LOW-LEAKAGE ON-CHIP CAPACITORS
    15.
    发明公开
    TECHNOLOGIES FOR LOW-LEAKAGE ON-CHIP CAPACITORS 审中-公开

    公开(公告)号：US20230317773A1

    公开(公告)日：2023-10-05

    申请号：US17711736

    申请日：2022-04-01

    Applicant: Intel Corporation

    Inventor： Sameer Shekhar ,  Amit K. Jain ,  Chin Lee Kuan

    IPC: H01L49/02 ,  H03H1/00

    CPC classification number: H01L28/92 ,  H03H1/0007 ,  H03H2001/0014

    Abstract: Technologies for low-leakage and low series resistance on-chip capacitors are disclosed. In the illustrative embodiment, each electrode of a capacitor is formed from two metal layers and vias between the metal layers. A high-k dielectric layer is between the metal layers. The electrodes are displaced relative to each other on the plane defined by the high-k dielectric layer. As a result, electric field lines of the capacitor are parallel to the high-k dielectric layer. The electrodes can be displaced from each other by more than the thickness of the high-k dielectric layer, reducing the leakage current through the high-k dielectric layer as compared to a capacitor with field lines perpendicular to the high-k dielectric layer. Such a capacitor may be used to provide power to circuits in a low-power state with little leakage current and/or may be used to absorb radiofrequency (RF) interference.

    APPARATUSES, METHODS, AND SYSTEMS WITH CROSS-COUPLING NOISE REDUCTION
    17.
    发明申请
    APPARATUSES, METHODS, AND SYSTEMS WITH CROSS-COUPLING NOISE REDUCTION 有权
    具有交叉耦合噪声减少的装置，方法和系统

    公开(公告)号：US20160181812A1

    公开(公告)日：2016-06-23

    申请号：US14575900

    申请日：2014-12-18

    Applicant: Intel Corporation

    Inventor： Amit K. Jain ,  Sameer Shekhar

    IPC: H02J4/00 ,  H03H7/48

    CPC classification number: H02J4/00 ,  H01F5/00 ,  H03H1/0007 ,  H03H7/00 ,  H03H7/09 ,  H03H7/1725 ,  H03H7/48 ,  H03H2001/0078

    Abstract: Embodiments include apparatuses, methods, and systems with cross-coupling noise reduction in circuits. In embodiments, a circuit may include a common inductor and a negatively coupled inductor pair connected or coupled between the first inductor and a first load and a second load. The negatively coupled inductor pair may include a first and a second inductor. The first inductor may be connected or coupled to the first load and the second inductor may be connected or coupled to the second load to reduce cross-coupling noise between the first load and the second load. Examples of passive structures that may be used to implement the circuit are also described. Other embodiments may also be described and claimed.

    Abstract translation: 实施例包括在电路中具有交叉耦合噪声降低的装置，方法和系统。 在实施例中，电路可以包括在第一电感器和第一负载和第二负载之间连接或耦合的公共电感器和负耦合电感器对。 负耦合电感器对可以包括第一和第二电感器。 第一电感器可以连接或耦合到第一负载，并且第二电感器可以连接或耦合到第二负载，以减少第一负载和第二负载之间的交叉耦合噪声。 还描述了可用于实现电路的无源结构的示例。 也可以描述和要求保护其他实施例。

    DEVICE, METHOD AND SYSTEM TO DETERMINE A MODE OF VOLTAGE REGULATION BASED ON PARASITICS OF A POWER DELIVERY NETWORK
    19.
    发明申请
    DEVICE, METHOD AND SYSTEM TO DETERMINE A MODE OF VOLTAGE REGULATION BASED ON PARASITICS OF A POWER DELIVERY NETWORK 有权

    公开(公告)号：US20220413536A1

    公开(公告)日：2022-12-29

    申请号：US17359413

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Amit K. Jain ,  Mauricio Aguilar Salas ,  Jonathan Douglas ,  Anant Deval

    IPC: G05F1/59 ,  G06F1/3203 ,  G05F1/575

    Abstract: Techniques and mechanisms for determining an operational mode of a voltage regulator. In an embodiment, an integrated circuit (IC) die is coupled to receive power from a voltage regulator (VR) via a power delivery network (PDN) which comprises circuitry in or on a substrate, such as that of a printed circuit board. The IC die receives from the substrate information indicating a characteristic of a parasitic impedance at the substrate. Based on the information, a controller unit at the IC die selects one of multiple VR modes which each correspond to a respective one of different parasitic impedance characteristics. The controller then signals the VR to provide the selected mode. In an embodiment one of the VR modes corresponds to a relatively high impedance, and also corresponds to a relatively stable sensitivity function in a frequency range above a control bandwidth.

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