公开(公告)号：US20230101723A1

公开(公告)日：2023-03-30

申请号：US18077142

申请日：2022-12-07

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Joseph STEIGERWALD ,  Jinhong SHIN ,  Vinay CHIKARMANE ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

公开(公告)号：US20200043850A1

公开(公告)日：2020-02-06

申请号：US16542960

申请日：2019-08-16

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Atul MADHAVAN ,  Christopher P. AUTH

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L29/78 ,  H01L23/522 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/092 ,  H01L21/308 ,  H01L29/66 ,  H01L27/11 ,  H01L29/08 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/762 ,  H01L49/02

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an ILD layer. The plurality of conductive interconnect lines includes a first interconnect line, and a second interconnect line immediately adjacent the first interconnect line and having a width different than a width of the first interconnect line. A third interconnect line is immediately adjacent the second interconnect line. A fourth interconnect line is immediately adjacent the third interconnect line and has a width the same as the width of the second interconnect line. A fifth interconnect line is immediately adjacent the fourth interconnect line and has a width the same as the width of the first interconnect line.

公开(公告)号：US20200027781A1

公开(公告)日：2020-01-23

申请号：US16509398

申请日：2019-07-11

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Ruth BRAIN ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.

公开(公告)号：US20190164814A1

公开(公告)日：2019-05-30

申请号：US15859418

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Ilsup JIN ,  Angelo KANDAS ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/06 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A conductive interconnect line is in a trench in the ILD layer, the conductive interconnect line having a first portion and a second portion, the first portion laterally adjacent to the second portion. A dielectric plug is between and laterally adjacent to the first and second portions of the conductive interconnect line, the dielectric plug comprising a metal oxide material.

公开(公告)号：US20250098258A1

公开(公告)日：2025-03-20

申请号：US18970265

申请日：2024-12-05

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Ilsup JIN ,  Angelo KANDAS ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H10B10/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

公开(公告)号：US20230144607A1

公开(公告)日：2023-05-11

申请号：US18093776

申请日：2023-01-05

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Tahir GHANI ,  Atul MADHAVAN ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H10B10/00 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

CPC classification number: H01L29/66545 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7843 ,  H01L27/0886 ,  H01L21/76232 ,  H01L29/6656 ,  H01L29/0653 ,  H01L21/823431 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L21/76816 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785 ,  H01L29/165 ,  H01L21/76846 ,  H01L21/76849 ,  H01L29/7845 ,  H01L21/76834 ,  H01L29/41791 ,  H01L21/76801 ,  H10B10/12 ,  H01L29/0649 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/0924 ,  H01L28/24 ,  H01L29/0847 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/7854 ,  H01L21/28518 ,  H01L23/5329 ,  H01L27/0207 ,  H01L28/20 ,  H01L29/41783 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823828 ,  H01L23/528 ,  H01L27/0922 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/7851 ,  H01L21/76883 ,  H01L21/76885 ,  H01L29/665 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

公开(公告)号：US20210234022A1

公开(公告)日：2021-07-29

申请号：US17227165

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Tahir GHANI ,  Atul MADHAVAN ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

公开(公告)号：US20210013323A1

公开(公告)日：2021-01-14

申请号：US17027568

申请日：2020-09-21

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Ilsup JIN ,  Angelo KANDAS ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

公开(公告)号：US20200044049A1

公开(公告)日：2020-02-06

申请号：US16537020

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Joseph STEIGERWALD ,  Jinhong SHIN ,  Vinay CHIKARMANE ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/167 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/02 ,  H01L29/417 ,  H01L49/02 ,  H01L27/02 ,  H01L23/532 ,  H01L21/285 ,  H01L29/51 ,  H01L29/08 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/311 ,  H01L21/308 ,  H01L21/28 ,  H01L21/033 ,  H01L29/06 ,  H01L29/165 ,  H01L23/522 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

公开(公告)号：US20190164818A1

公开(公告)日：2019-05-30

申请号：US15859417

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Ruth BRAIN ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.