公开(公告)号：US20230402449A1

公开(公告)日：2023-12-14

申请号：US18457453

申请日：2023-08-29

申请人： Intel Corporation

发明人： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Adam Clay Faust ,  Frank Patrick O'Mahony ,  Ayan Kar ,  Rui Ma

IPC分类号： H01L27/02

CPC分类号： H01L27/0292 ,  H01L27/0288 ,  H01L27/0255

摘要： Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

公开(公告)号：US11837641B2

公开(公告)日：2023-12-05

申请号：US16719281

申请日：2019-12-18

申请人： Intel Corporation

发明人： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC分类号： H01L29/41 ,  H01L29/417 ,  H01L25/18 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L25/18 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/7853 ,  H01L2029/7858

摘要： Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US11996403B2

公开(公告)日：2024-05-28

申请号：US16713656

申请日：2019-12-13

申请人： Intel Corporation

发明人： Nidhi Nidhi ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Ting Chang ,  Babak Fallahazad ,  Tanuj Trivedi ,  Jeong Dong Kim ,  Ayan Kar ,  Benjamin Orr

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L27/0255 ,  H01L29/0673 ,  H01L29/66136

摘要： Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a source. The source has a first conductivity type and a first insulator separates the source from the semiconductor substrate. The semiconductor device further comprises a drain. The drain has a second conductivity type that is opposite from the first conductivity type, and a second insulator separates the drain from the semiconductor substrate. In an embodiment, the semiconductor further comprises a semiconductor body between the source and the drain, where the semiconductor body is spaced away from the semiconductor substrate.

公开(公告)号：US20240170581A1

公开(公告)日：2024-05-23

申请号：US17992057

申请日：2022-11-22

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Ayan Kar ,  Patrick Morrow ,  Charles C. Kuo ,  Nicholas A. Thomson ,  Benjamin Orr ,  Kalyan C. Kolluru ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC分类号： H01L29/861 ,  H01L27/02 ,  H01L27/06 ,  H01L29/06

CPC分类号： H01L29/8611 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0649

摘要： An integrated circuit structure includes a sub-fin having at least a first portion that is doped with a first type of dopant, and a second portion that is doped with a second type of dopant. A PN junction is between the first and second portions of the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. A first contact and a second contact comprise conductive material. In an example, the first contact and the second contact are respectively in contact with the first portion and the second portion of the sub-fin. A diode is formed based on the PN junction between the first and second portions, where the first contact is an anode contact of the diode, and the second contact is a cathode contact of the diode.

公开(公告)号：US20240088134A1

公开(公告)日：2024-03-14

申请号：US17943815

申请日：2022-09-13

申请人： Intel Corporation

发明人： Nicholas A. Thomson ,  Ayan Kar ,  Kalyan C. Kolluru ,  Mauro J. Kobrinsky

IPC分类号： H01L27/02 ,  H01L21/8234

CPC分类号： H01L27/0266 ,  H01L21/823418 ,  H01L21/823481

摘要： An integrated circuit structure includes laterally adjacent first and second devices. The first device has (i) a first diffusion region, (ii) a first body including semiconductor material extending laterally from the first diffusion region, and (iii) a first gate structure on the first body. The first diffusion region has a first lower section that extends below a lower surface of the first gate structure, the first lower section having a first height. The second device has (i) a second diffusion region, (ii) a second body including semiconductor material extending laterally from the second diffusion region, and (iii) a second gate structure on the second body. The second diffusion region has a second lower section that extends below a lower surface of the second gate structure, the second lower section having a second height. In an example, the first height is at least 2 nanometers greater than the second height.

公开(公告)号：US20240088133A1

公开(公告)日：2024-03-14

申请号：US17943840

申请日：2022-09-13

申请人： INTEL CORPORATION

发明人： Nicholas A. Thomson ,  Ayan Kar ,  Kalyan C. Kolluru ,  Mauro J. Kobrinksy ,  Benjamin Orr

IPC分类号： H01L27/02 ,  H01L23/528 ,  H01L29/06 ,  H01L29/861

CPC分类号： H01L27/0255 ,  H01L23/5283 ,  H01L27/0266 ,  H01L29/0673 ,  H01L29/8611

摘要： An integrated circuit structure includes a sub-fin having a first type of dopant, a first diffusion region having the first type of dopant and in contact with the sub-fin, and a second diffusion region and a third diffusion region having a second type of dopant and in contact with the sub-fin. The first type of dopant is one of p-type or n-type dopant, and where the second type of dopant is the other of the p-type or n-type dopant. A first body of semiconductor material extends from the second diffusion region to the third diffusion region, and a second body of semiconductor material extends from the first diffusion region towards the second diffusion region. The first diffusion region is a tap diffusion region contacting the sub-fin. In an example, the first diffusion region facilitates formation of a diode for electrostatic discharge (ESD) protection of the integrated circuit structure.

公开(公告)号：US20240088132A1

公开(公告)日：2024-03-14

申请号：US17943819

申请日：2022-09-13

申请人： Intel Corporation

发明人： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Ayan Kar ,  Chu-Hsin Liang ,  Benjamin Orr ,  Biswajeet Guha ,  Brian Greene ,  Chung-Hsun Lin ,  Sabih U. Omar ,  Sameer Jayanta Joglekar

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/861

CPC分类号： H01L27/0255 ,  H01L29/0673 ,  H01L29/8611

摘要： An integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. A first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. In an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a PN junction of a diode. For example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.

公开(公告)号：US20240088131A1

公开(公告)日：2024-03-14

申请号：US17943812

申请日：2022-09-13

申请人： Intel Corporation

发明人： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Ayan Kar ,  Mauro J. Kobrinsky

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/861

CPC分类号： H01L27/0255 ,  H01L27/0266 ,  H01L29/0673 ,  H01L29/8611

摘要： An integrated circuit structure includes a sub-fin having at least a portion that is doped with a first type of dopant, and a diffusion region doped with a second type of dopant. The diffusion region is in contact with the sub-fin and extends upward from the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. In an example, a first conductive contact is above and on the diffusion region, and a second conductive contact is in contact with the portion of the sub-fin. In an example, the diffusion region is at least a part of one of an anode or a cathode of a diode, and the portion of the sub-fin is at least a part of the other of the anode or the cathode of the diode.

公开(公告)号：US11824116B2

公开(公告)日：2023-11-21

申请号：US16719222

申请日：2019-12-18

申请人： Intel Corporation

发明人： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Ayan Kar ,  Nicholas Thomson ,  Benjamin Orr ,  Nathan Jack ,  Kalyan Kolluru ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L29/7831 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/785

摘要： Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.

公开(公告)号：US11791331B2

公开(公告)日：2023-10-17

申请号：US17526199

申请日：2021-11-15

申请人： Intel Corporation

发明人： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Adam Clay Faust ,  Frank Patrick O'Mahony ,  Ayan Kar ,  Rui Ma

IPC分类号： H01L27/02

CPC分类号： H01L27/0292 ,  H01L27/0255 ,  H01L27/0288

摘要： Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.