公开(公告)号：US20220157374A1

公开(公告)日：2022-05-19

申请号：US17666452

申请日：2022-02-07

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Bill NALE

IPC: G11C11/406 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4093 ,  G11C29/02

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

公开(公告)号：US20190229473A1

公开(公告)日：2019-07-25

申请号：US16370665

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Jaejin LEE ,  Jun LIAO ,  Xiang LI ,  Christopher E. COX

IPC: H01R13/6595 ,  H01R13/6581 ,  H05K9/00 ,  H01R12/72 ,  H05K1/11

Abstract: A device includes a printed circuit board (PCB) and a shield for the PCB. The shield can reduce high frequency electromagnetic frequency (EMF) noise generated by one or more components of the PCB. The PCB includes pads to interface with a corresponding connector. For example, for a dual inline memory module (DIMM) PCB, the PCB includes pads to insert into a DIMM connector. The shield includes a gap in its perimeter that aligns with clips in the corresponding connector. The gaps will correspond to similar features of the PCB that interface with the corresponding connector to allow the shield to attach to the PCB. The shield includes lock fingers to extend from a connector-facing edge of the shield to interface with the corresponding connector to align the shield with the corresponding connector.

公开(公告)号：US20190228813A1

公开(公告)日：2019-07-25

申请号：US16370578

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Bill NALE ,  Christopher E. COX

IPC: G11C11/406 ,  G11C11/4096 ,  G06F3/06

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US20190163393A1

公开(公告)日：2019-05-30

申请号：US16264591

申请日：2019-01-31

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Christopher P. MOZAK

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes a memory controller having an interface to communicate with a memory. The memory controller comprising logic circuitry to specify one of multiple possible write values to the memory during a write operation with multiple bits of a command that is sent on a command address bus that emanates from the interface. The memory to write any one of the possible write values into its storage cells while the memory interface is in a power saving state wherein the specified one write value is not articulated by the memory controller on a data bus of the interface as part of the write operation.

公开(公告)号：US20180254079A1

公开(公告)日：2018-09-06

申请号：US15911068

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Uksong KANG ,  Nagi ABOULENEIN

IPC: G11C11/408 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52

Abstract: A multi-die memory device having fixed bandwidth interfaces can selectively connect portions of the interfaces of the multiple memory dies as a memory channel for the multi-die device. The selective application of the interface bits of the memory dies enables the application of ECC (error checking and correction) in memory devices that otherwise have insufficient connectors to exchange ECC information. The device includes circuitry to selectively apply CAS (column address select) signals to the memory dies to selectively connect the connectors of the memory dies. CAS selection can provide various configurations in which selected bits of a first memory die interface are combined with selected bit or bits of a second memory die interface to provide the device interface. The memory dies can operate in byte mode to apply only half of their data I/O (input/output) interface, with CAS doubled up to provide access to the memory arrays.

公开(公告)号：US20170077928A1

公开(公告)日：2017-03-16

申请号：US15359573

申请日：2016-11-22

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Nadav BONEN ,  Christopher E. COX ,  Alexey KOSTINSKY

IPC: H03K19/00 ,  G06F13/40 ,  G06F3/06

CPC classification number: H03K19/0005 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/4086 ,  H03K19/0008 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

Abstract translation: 存储器子系统包括多器件封装，其包括被组织为多级存储器的多个存储器件。 用于存储器子系统的控制单元向存储器的一些或全部行同时发送存储器访问命令，并且触发接收存储器访问命令的所有存储器等级的一部分以改变管芯终端（ODT）设置。 选择其中一个行执行存储器访问命令，并且在所有等级触发以改变ODT设置的情况下执行命令具有改变的ODT设置。

公开(公告)号：US20210151095A1

公开(公告)日：2021-05-20

申请号：US17157826

申请日：2021-01-25

Applicant: Intel Corporation

Inventor： Bill NALE ,  Christopher E. COX

IPC: G11C11/406 ,  G11C11/4096 ,  G06F3/06

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US20200159429A1

公开(公告)日：2020-05-21

申请号：US16702359

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Dean-Dexter R. EUGENIO ,  Arvind KUMAR ,  John R. GOLES ,  Christopher E. COX

IPC: G06F3/06 ,  G06F11/22 ,  G06F13/16

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

公开(公告)号：US20190252009A1

公开(公告)日：2019-08-15

申请号：US16277797

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Uksong KANG ,  Christopher E. COX

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C16/10 ,  G11C11/408 ,  H04L29/06 ,  G11C11/4096 ,  G11C11/4093

CPC classification number: G11C7/10 ,  G06K9/00006 ,  G11C7/22 ,  G11C11/40607 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096 ,  G11C16/10 ,  G11C2207/229 ,  H04L29/06

Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.

公开(公告)号：US20190096468A1

公开(公告)日：2019-03-28

申请号：US15716485

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Christopher P. MOZAK ,  Christopher E. COX ,  Yan FU ,  Robert J. FRIAR ,  Hsien-Pao YANG

IPC: G11C11/4072 ,  G06F3/06

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.