公开(公告)号：US10922161B2

公开(公告)日：2021-02-16

申请号：US16203578

申请日：2018-11-28

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Bryan White ,  Ankur Shah ,  Murali Ramadoss ,  David Puffer ,  Altug Koker ,  Aditya Navale ,  Mahesh Natu

IPC: G06F11/00 ,  G06F11/07

Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

公开(公告)号：US10769078B2

公开(公告)日：2020-09-08

申请号：US16453995

申请日：2019-06-26

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

IPC: G06F12/109 ,  G06F11/07 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US10726517B2

公开(公告)日：2020-07-28

申请号：US16293044

申请日：2019-03-05

Applicant: Intel Corporation

Inventor： Altug Koker ,  Ingo Wald ,  David Puffer ,  Subramaniam M. Maiyuran ,  Prasoonkumar Surti ,  Balaji Vembu ,  Guei-Yuan Lueh ,  Murali Ramadoss ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06T1/20 ,  G06F9/48

Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.

公开(公告)号：US20200210238A1

公开(公告)日：2020-07-02

申请号：US16726341

申请日：2019-12-24

Applicant: Intel Corporation

Inventor： Abhishek R Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06F9/48 ,  G06F1/329

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US10565676B2

公开(公告)日：2020-02-18

申请号：US15488547

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Adam T. Lake ,  Guei-Yuan Lueh ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Altug Koker ,  Subramaniam M. Maiyuran ,  Eric C. Samson ,  David J. Cowperthwaite ,  Zhi Wang ,  Kun Tian ,  David Puffer ,  Brian T. Lewis

IPC: G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.

公开(公告)号：US20200026514A1

公开(公告)日：2020-01-23

申请号：US16526147

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kamal Sinha ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Guei-Yuan Lueh ,  David Puffer ,  Supratim Pal ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

IPC: G06F9/30 ,  G06F9/38 ,  G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06F9/46 ,  G09G5/36

Abstract: In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

公开(公告)号：US12204487B2

公开(公告)日：2025-01-21

申请号：US18415052

申请日：2024-01-17

Applicant: Intel Corporation

Inventor： Altug Koker ,  Varghese George ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek R. Appu ,  Niranjan Cooray ,  Nicolas Galoppo Von Borries ,  Mike MacPherson ,  Subramaniam Maiyuran ,  ElMoustapha Ould-Ahmed-Vall ,  David Puffer ,  Vasanth Ranganathan ,  Joydeep Ray ,  Ankur N. Shah ,  Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  Saurabh Tangri

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments are generally directed to graphics processor data access and sharing. An embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.

公开(公告)号：US12067641B2

公开(公告)日：2024-08-20

申请号：US17749266

申请日：2022-05-20

Applicant: Intel Corporation

Inventor： Altug Koker ,  Ingo Wald ,  David Puffer ,  Subramaniam M. Maiyuran ,  Prasoonkumar Surti ,  Balaji Vembu ,  Guei-Yuan Lueh ,  Murali Ramadoss ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06T1/20 ,  G06F9/3009 ,  G06F9/30185 ,  G06F9/3851 ,  G06F9/461 ,  G06F9/4843

Abstract: One embodiment provides a parallel processor comprising a memory interface and a processing array coupled with the memory interface. The processing array is configured to address memory accessed via the memory interface via a virtual address mapping and includes circuitry to resolve a page fault for the virtual address mapping, wherein each of the multiple compute blocks is separately preemptable.

公开(公告)号：US20240095201A1

公开(公告)日：2024-03-21

申请号：US18459311

申请日：2023-08-31

Applicant: Intel Corporation

Inventor： David Puffer ,  Ankur Shah ,  Niranjan Cooray ,  Bryan White ,  Balaji Vembu ,  Hema Chand Nalluri ,  Kritika Bala

IPC: G06F13/24 ,  G06F13/16

CPC classification number: G06F13/24 ,  G06F13/1668 ,  G06T1/20

Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

公开(公告)号：US20230259458A1

公开(公告)日：2023-08-17

申请号：US18168157

申请日：2023-02-13

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06F12/0802 ,  G06F12/0855 ,  G06F12/0806 ,  G06F12/0846 ,  G06F12/0868 ,  G06T1/60 ,  G06F12/126

CPC classification number: G06F12/0877 ,  G06F12/0802 ,  G06F12/0855 ,  G06F12/0806 ,  G06F12/0848 ,  G06F12/0868 ,  G06T1/60 ,  G06F12/126 ,  G06F12/0893

Abstract: One embodiment provides circuitry coupled with cache memory and a memory interface, the circuitry to compress compute data at multiple cache line granularity, and a processing resource coupled with the memory interface and the cache memory. The processing resource is configured to perform a general-purpose compute operation on compute data associated with multiple cache lines of the cache memory. The circuitry is configured to compress the compute data before a write of the compute data via the memory interface to the memory bus, in association with a read of the compute data associated with the multiple cache lines via the memory interface, decompress the compute data, and provide the decompressed compute data to the processing resource.