公开(公告)号：US20230197520A1

公开(公告)日：2023-06-22

申请号：US17557579

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Yi SHI ,  Omkar KARHADE ,  Shawna M. LIFF ,  Zhihua ZOU ,  Ryan MACKIEWICZ ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Arnab SARKAR

IPC: H01L21/822 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/822 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/97 ,  H01L2924/15311

Abstract: Embodiments herein relate to systems, apparatuses, or processes for attaching dummy dies to a wafer that includes a plurality of active dies, where the dummy dies are placed along or in dicing streets where the wafer is to be cut during singulation. In embodiments, the dummy dies may be attached to the wafer using a die attach film, or may be attached using hybrid bonding. Other embodiments may be described and/or claimed.

公开(公告)号：US20230040850A1

公开(公告)日：2023-02-09

申请号：US17972340

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

IPC: H01L23/522 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20210202380A1

公开(公告)日：2021-07-01

申请号：US17200700

申请日：2021-03-12

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Poh Boon KHOO ,  Eng Huat GOH ,  Amruthavalli Pallavi ALUR ,  Debendra MALLIK

IPC: H01L23/522 ,  H01L23/00

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

公开(公告)号：US20200350181A1

公开(公告)日：2020-11-05

申请号：US16915290

申请日：2020-06-29

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/16

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20200051899A1

公开(公告)日：2020-02-13

申请号：US16059535

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Sanka GANESAN ,  Pilin LIU ,  Shawna LIFF ,  Sri Chaitra CHAVALI ,  Sandeep GAAN ,  Jimin YAO ,  Aastha UPPAL

IPC: H01L23/498 ,  H01L23/28 ,  H01L23/34 ,  H01L23/538 ,  H01L23/532

Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.

公开(公告)号：US20190341271A1

公开(公告)日：2019-11-07

申请号：US16515981

申请日：2019-07-18

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/16 ,  H01L25/18

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20190279938A1

公开(公告)日：2019-09-12

申请号：US16461316

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Vipul Vijay MEHTA ,  Eric Jin LI ,  Sanka GANESAN ,  Debendra MALLIK ,  Robert Leon SANKMAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

公开(公告)号：US20250029929A1

公开(公告)日：2025-01-23

申请号：US18907985

申请日：2024-10-07

Applicant: Intel Corporation

Inventor： Sanka GANESAN ,  Kevin MCCARTHY ,  Leigh M. TRIBOLET ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

公开(公告)号：US20240136278A1

公开(公告)日：2024-04-25

申请号：US18400784

申请日：2023-12-29

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Poh Boon KHOO ,  Eng Huat GOH ,  Amruthavalli Pallavi ALUR ,  Debendra MALLIK

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2924/01029

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

公开(公告)号：US20230360994A1

公开(公告)日：2023-11-09

申请号：US18222855

申请日：2023-07-17

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Digvijay RAORANE

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/495

CPC classification number: H01L23/367 ,  H01L23/5386 ,  H01L23/3107 ,  H01L21/565 ,  H01L24/08 ,  H01L21/4853 ,  H01L24/83 ,  H01L24/16 ,  H01L21/56 ,  H01L24/20 ,  H01L24/24 ,  H01L24/29 ,  H01L23/49568 ,  H01L23/3128 ,  H01L2224/02371

Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.