公开(公告)号：US20180300964A1

公开(公告)日：2018-10-18

申请号：US15488914

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： BARATH LAKSHAMANAN ,  LINDA L. HURD ,  BEN J. ASHBAUGH ,  ELMOUSTAPHA OULD-AHMED-VALL ,  LIWEI MA ,  JINGYI JIN ,  JUSTIN E. GOTTSCHLICH ,  CHANDRASEKARAN SAKTHIVEL ,  MICHAEL S. STRICKLAND ,  BRIAN T. LEWIS ,  LINDSEY KUPER ,  ALTUG KOKER ,  ABHISHEK R. APPU ,  PRASOONKUMAR SURTI ,  JOYDEEP RAY ,  BALAJI VEMBU ,  JAVIER S. TUREK ,  NAILA FAROOQUI

IPC: G07C5/00 ,  G05D1/00 ,  G01C21/34 ,  G08G1/052 ,  G08G1/01 ,  H04W28/08 ,  G06N99/00

CPC classification number: G07C5/008 ,  B60W30/00 ,  G01C21/34 ,  G01S19/13 ,  G05D1/0088 ,  G05D2201/0213 ,  G06F9/5027 ,  G06F2209/509 ,  G06N20/00 ,  G08G1/0112 ,  G08G1/012 ,  G08G1/052 ,  H04L43/0852 ,  H04L67/12 ,  H04W28/08

Abstract: One embodiment provides for a computing device within an autonomous vehicle, the compute device comprising a wireless network device to enable a wireless data connection with an autonomous vehicle network, a set of multiple processors including a general-purpose processor and a general-purpose graphics processor, the set of multiple processors to execute a compute manager to manage execution of compute workloads associated with the autonomous vehicle, the compute workload associated with autonomous operations of the autonomous vehicle, and offload logic configured to execute on the set of multiple processors, the offload logic to determine to offload one or more of the compute workloads to one or more autonomous vehicles within range of the wireless network device.

公开(公告)号：US20230421738A1

公开(公告)日：2023-12-28

申请号：US18347278

申请日：2023-07-05

Applicant: Intel Corporation

Inventor： MAYURESH VARERKAR ,  STANLEY BARAN ,  MICHAEL APODACA ,  PRASOONKUMAR SURTI ,  ATSUO KUWAHARA ,  NARAYAN BISWAL ,  JILL BOYCE ,  YI-JEN CHIU ,  GOKCEN CILINGIR ,  BARNAN DAS ,  ATUL DIVEKAR ,  SRIKANTH POTLURI ,  NILESH SHAH ,  ARCHIE SHARMA

IPC: H04N13/111 ,  H04N19/597 ,  G06F9/38 ,  G06F3/01 ,  G06N20/00

CPC classification number: H04N13/111 ,  H04N19/597 ,  G06F9/3877 ,  G06F3/012 ,  G06N20/00

Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.

公开(公告)号：US20230297415A1

公开(公告)日：2023-09-21

申请号：US17699058

申请日：2022-03-18

Applicant: INTEL CORPORATION

Inventor： PAWEL MAJEWSKI ,  PRASOONKUMAR SURTI ,  TOBIAS ZIRR

IPC: G06F9/48 ,  G06T1/20 ,  G06F9/30

CPC classification number: G06F9/4843 ,  G06T1/20 ,  G06F9/30189

Abstract: Apparatus and method for scheduling inference tasks. For example, one embodiment of an apparatus comprises: a plurality of compute units (CUs) to execute inferencing routines, an inferencing routine comprising a plurality of phases, at least one CU comprising execution circuitry configurable to operate in a single instruction multiple data (SIMD) mode or a single instruction multiple thread (SIMT) mode; and dispatching hardware logic to determine whether a current phase of an inferencing routine is to be executed in the SIMD mode or the SIMT mode, and to dispatch instructions of the current phase for execution by the execution circuitry of a CU in accordance with the SIMD mode or the SIMT mode, respectively.

公开(公告)号：US20210272349A1

公开(公告)日：2021-09-02

申请号：US17306769

申请日：2021-05-03

Applicant: Intel Corporation

Inventor： TRAVIS SCHLUESSLER ,  ZACK WATERS ,  MICHAEL APODACA ,  DANIEL JOHNSTON ,  JASON SURPRISE ,  PRASOONKUMAR SURTI ,  SUBRAMANIAM MAIYURAN ,  PETER DOYLE ,  SAURABH SHARMA ,  ANKUR SHAH ,  MURALI RAMADOSS

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US20210201558A1

公开(公告)日：2021-07-01

申请号：US16728375

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： KAROL SZERSZEN ,  PRASOONKUMAR SURTI ,  GABOR LIKTOR ,  KARTHIK VAIDYANATHAN ,  SVEN WOOP

IPC: G06T15/06 ,  G06T15/08 ,  G06T15/00 ,  G06T17/10 ,  G06T1/20

Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.

公开(公告)号：US20200211252A1

公开(公告)日：2020-07-02

申请号：US16235893

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： PRASOONKUMAR SURTI ,  CARSTEN BENTHIN ,  KARTHIK VAIDYANATHAN ,  PHILIP LAWS ,  SCOTT JANUS ,  SVEN WOOP

IPC: G06T15/00 ,  G06T15/06

Abstract: Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.

公开(公告)号：US20200051309A1

公开(公告)日：2020-02-13

申请号：US16537140

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： HUGUES LABBE ,  DARREL PALKE ,  SHERINE ABDELHAK ,  JILL BOYCE ,  VARGHESE GEORGE ,  SCOTT JANUS ,  ADAM LAKE ,  ZHIJUN LEI ,  ZHENGMIN LI ,  MIKE MACPHERSON ,  CARL MARSHALL ,  SELVAKUMAR PANNEER ,  PRASOONKUMAR SURTI ,  KARTHIK VEERAMANI ,  DEEPAK VEMBAR ,  VALLABHAJOSYULA SRINIVASA SOMAYAZULU

IPC: G06T15/00 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/40 ,  G06T17/20

Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

公开(公告)号：US20190041961A1

公开(公告)日：2019-02-07

申请号：US16144538

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： KINCHIT DESAI ,  SANJEEV JAHAGIRDAR ,  PRASOONKUMAR SURTI ,  JOYDEEP RAY

IPC: G06F1/32 ,  G06N3/08 ,  G06N3/04

Abstract: Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference. An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero.

公开(公告)号：US20230377209A1

公开(公告)日：2023-11-23

申请号：US18322194

申请日：2023-05-23

Applicant: Intel Corporation

Inventor： ABHISHEK R. APPU ,  PRASOONKUMAR SURTI ,  JILL BOYCE ,  SUBRAMANIAM MAIYURAN ,  MICHAEL APODACA ,  ADAM T. LAKE ,  JAMES HOLLAND ,  VASANTH RANGANATHAN ,  ALTUG KOKER ,  LIDONG XU ,  NIKOS KABURLASOS

IPC: G06T9/00 ,  G06T15/00 ,  G06N3/045

CPC classification number: G06T9/002 ,  G06T9/007 ,  G06T15/005 ,  G06T9/008 ,  G06N3/045

Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.

公开(公告)号：US20230360307A1

公开(公告)日：2023-11-09

申请号：US18310015

申请日：2023-05-01

Applicant: Intel Corporation

Inventor： HUGUES LABBE ,  DARREL PALKE ,  SHERINE ABDELHAK ,  JILL BOYCE ,  VARGHESE GEORGE ,  SCOTT JANUS ,  ADAM LAKE ,  ZHIJUN LEI ,  ZHENGMIN LI ,  MIKE MACPHERSON ,  CARL MARSHALL ,  SELVAKUMAR PANNEER ,  PRASOONKUMAR SURTI ,  KARTHIK VEERAMANI ,  DEEPAK VEMBAR ,  VALLABHAJOSYULA SRINIVASA SOMAYAZULU

IPC: G06T15/00 ,  G06N3/08 ,  G06T17/20 ,  G06T1/60 ,  G06T15/40 ,  G06T1/20

CPC classification number: G06T15/005 ,  G06N3/08 ,  G06T17/20 ,  G06T1/60 ,  G06T15/40 ,  G06T1/20

Abstract: One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.