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    SELF-ALIGNED VIA
    11.
    发明申请
    SELF-ALIGNED VIA 审中-公开

    公开(公告)号：US20190311984A1

    公开(公告)日：2019-10-10

    申请号：US16464941

    申请日：2016-12-29

    申请人： Intel Corporation

    发明人： Kevin L. Lin ,  Robert L. Bristol ,  Rami Hourani ,  James M. Blackwell

    IPC分类号： H01L23/522 ,  H01L21/768

    摘要： There is disclosed in an example an integrated circuit, including: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; a dielectric plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect; and a dielectric cap covering the dielectric plug.

    METAL-INSULATOR-METAL CAPACITOR FORMATION TECHNIQUES
    13.
    发明申请
    METAL-INSULATOR-METAL CAPACITOR FORMATION TECHNIQUES 审中-公开
    金属绝缘体 - 金属电容器形成技术

    公开(公告)号：US20150155349A1

    公开(公告)日：2015-06-04

    申请号：US14622157

    申请日：2015-02-13

    申请人： INTEL CORPORATION

    发明人： Mauro J. Kobrinsky ,  Robert L. Bristol ,  Michael C. Mayberry

    IPC分类号： H01L49/02

    CPC分类号： H01L28/60 ,  H01L21/0337 ,  H01L27/224 ,  H01L28/82

    摘要： Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes.

    摘要翻译： 公开了用于提供具有大体波形轮廓的MIM电容器的技术和结构。 使用牺牲性自组织材料提供波纹形状，其有效地产生响应于被形成MIM电容器的介电材料的处理（热或其它合适的刺激）的图案。 自组织材料可以是例如响应于热或其它刺激而分离成两个交替相的定向自组装材料层，其中相中的一个相可以相对于另一相被选择性地蚀刻到 提供所需的图案。 在另一个例子中，自组织材料是在加热时聚结成孤岛的材料层。 根据本公开将会理解，所公开的技术可以用于例如增加每单位面积的电容，其可以通过蚀刻更深的电容器沟槽/孔来缩放。

    Magneto-electric spin orbit (MESO) structures having functional oxide vias
    16.
    发明授权
    Magneto-electric spin orbit (MESO) structures having functional oxide vias 有权

    公开(公告)号：US10957844B2

    公开(公告)日：2021-03-23

    申请号：US16346872

    申请日：2016-12-23

    申请人： Intel Corporation

    发明人： Jasmeet S. Chawla ,  Sasikanth Manipatruni ,  Robert L. Bristol ,  Chia-Ching Lin ,  Dmitri E. Nikonov ,  Ian A. Young

    IPC分类号： H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L43/00 ,  H03K19/18

    摘要： Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.

    Photobucket floor colors with selective grafting
    17.
    发明授权
    Photobucket floor colors with selective grafting 有权

    公开(公告)号：US10892184B2

    公开(公告)日：2021-01-12

    申请号：US16317015

    申请日：2016-09-30

    申请人： Intel Corporation

    发明人： Robert L. Bristol ,  Kevin L. Lin ,  James M. Blackwell ,  Rami Hourani ,  Eungnak Han

    IPC分类号： H01L21/768 ,  H01L21/027 ,  H01L21/311

    摘要： Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.

    Surface-aligned lithographic patterning approaches for back end of line (BEOL) interconnect fabrication
    18.
    发明授权
    Surface-aligned lithographic patterning approaches for back end of line (BEOL) interconnect fabrication 有权

    公开(公告)号：US10796909B2

    公开(公告)日：2020-10-06

    申请号：US16343385

    申请日：2016-12-02

    申请人： Intel Corporation

    发明人： Robert L. Bristol ,  Kevin L. Lin ,  James M. Blackwell

    IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/768

    摘要： Surface-aligned lithographic patterning approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, an integrated circuit structure includes a substrate. A plurality of alternating first and second conductive lines is along a first direction of a back end of line (BEOL) metallization layer in a first inter-layer dielectric (ILD) layer above the substrate. A conductive via is on and electrically coupled to one of the conductive lines of the plurality of alternating first and second conductive lines, the conductive via centered over the one of the conductive lines. A second ILD layer is above plurality of alternating first and second conductive lines and laterally adjacent to the conductive via. The second ILD layer has an uppermost surface substantially co-planar with the flat top surface of the conductive via.