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公开(公告)号：US20200293456A1
公开(公告)日：2020-09-17
申请号：US16354859
申请日：2019-03-15
Applicant: Intel Corporation
Inventor： MURALI RAMADOSS , VIKRANTH VEMULAPALLI , NIRAN COORAY , WILLIAM B. SADLER , JONATHAN D. PEARCE , MARIAN ALIN PETRE , BEN ASHBAUGH , ELMOUSTAPHA OULD-AHMED-VALL , NICOLAS GALOPPO VON BORRIES , ALTUG KOKER , ARAVINDH ANANTARAMAN , SUBRAMANIAM MAIYURAN , VARGHESE GEORGE , SUNGYE KIM , ANDREI VALENTIN
IPC: G06F12/1009 , G06N20/00
Abstract: Methods and apparatus relating to predictive page fault handling. In an example, an apparatus comprises a processor to receive a virtual address that triggered a page fault for a compute process, check a virtual memory space for a virtual memory allocation for the compute process that triggered the page fault and manage the page fault according to one of a first protocol in response to a determination that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the compute process, or a second protocol in response to a determination that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the compute process. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20160140686A1
公开(公告)日：2016-05-19
申请号：US14543982
申请日：2014-11-18
Applicant: Intel Corporation
Inventor： GUEI-YUAN LUEH , SUBRAMANIAM MAIYURAN , WEI-YU CHEN , KAIYU CHEN
IPC: G06T1/20
CPC classification number: G06F9/462 , G06F9/30043 , G06F9/30076 , G06F9/3009 , G06F9/3851
Abstract: Systems and methods may provide for inserting one or more preemption instructions while compiling a computer program. The one or more preemption instructions being inserted within a preemption window in the computer program reduces the number of live registers at each preemption instruction position. Further, the preemption instruction instructs which registers are to be saved at a particular program position, typically the registers that are live at that program position. The compiled program may be run in an execution unit. A preemption request may be made to the execution unit and executed at a next available preemption instruction in the program being run in the execution unit.
Abstract translation: 系统和方法可以提供在编译计算机程序时插入一个或多个抢占指令。 计算机程序中的抢占窗口内插入的一个或多个抢占指令减少了每个抢占指令位置的实时寄存器数量。 此外，抢占指令指示哪些寄存器将被保存在特定的程序位置，通常是存在于该程序位置的寄存器。 编译的程序可以在执行单元中运行。 可以对执行单元进行抢占请求，并且在执行单元中运行的程序中的下一个可用抢占指令下执行抢占请求。
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公开(公告)号：US20240053985A1
公开(公告)日：2024-02-15
申请号：US18485089
申请日：2023-10-11
Applicant: Intel Corporation
Inventor： SUBRAMANIAM MAIYURAN , VARGHESE GEORGE , JOYDEEP RAY , ASHUTOSH GARG , JORGE PARRA , SHUBH SHAH , SHUBRA MARWAHA
CPC classification number: G06F9/3001 , G06F9/5011 , G06F17/16 , G06F9/3013 , G06F9/30036
Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a shared local memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive an instruction to initiate a matrix multiplication operation, write a first set of matrix data into a first set of registers, and share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation. Other embodiments may be described and claimed.
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公开(公告)号：US20230377209A1
公开(公告)日：2023-11-23
申请号：US18322194
申请日：2023-05-23
Applicant: Intel Corporation
Inventor： ABHISHEK R. APPU , PRASOONKUMAR SURTI , JILL BOYCE , SUBRAMANIAM MAIYURAN , MICHAEL APODACA , ADAM T. LAKE , JAMES HOLLAND , VASANTH RANGANATHAN , ALTUG KOKER , LIDONG XU , NIKOS KABURLASOS
CPC classification number: G06T9/002 , G06T9/007 , G06T15/005 , G06T9/008 , G06N3/045
Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.
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公开(公告)号：US20220366630A1
公开(公告)日：2022-11-17
申请号：US17876358
申请日：2022-07-28
Applicant: Intel Corporation
Inventor： TRAVIS SCHLUESSLER , ZACK WATERS , MICHAEL APODACA , DANIEL JOHNSTON , JASON SURPRISE , PRASOONKUMAR SURTI , SUBRAMANIAM MAIYURAN , PETER DOYLE , SAURABH SHARMA , ANKUR SHAH , MURALI RAMADOSS
Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.
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Patent Agency Ranking
公开(公告)号：US20220066931A1
公开(公告)日：2022-03-03
申请号：US17310540
申请日：2020-03-14
Applicant: INTEL CORPORATION
Inventor： JOYDEEP RAY , NIRANJAN COORAY , SUBRAMANIAM MAIYURAN , ALTUG KOKER , PRASOONKUMAR SURTI , VARGHESE GEORGE , VALENTIN ANDREI , ABHISHEK APPU , GUADALUPE GARCIA , PATTABHIRAMAN K , SUNGYE KIM , SANJAY KUMAR , PRATIK MAROLIA , ELMOUSTAPHA OULD-AHMED-VALL , VASANTH RANGANATHAN , WILLIAM SADLER , LAKSHMINARAYANAN STRIRAMASSARMA
IPC: G06F12/0802
Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.
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公开(公告)号：US20200293488A1
公开(公告)日：2020-09-17
申请号：US16354782
申请日：2019-03-15
Applicant: Intel Corporation
Inventor： JOYDEEP RAY , ARAVINDH ANANTARAMAN , ABHISHEK R. APPU , ALTUG KOKER , ELMOUSTAPHA OULD-AHMED-VALL , VALENTIN ANDREI , SUBRAMANIAM MAIYURAN , NICOLAS GALAPPO VON BORRIES , VARGHESE GEORGE , MIKE MACPHERSON , BEN ASHBAUGH , MURALI RAMADOSS , VIKRANTH VEMULAPALLI , WILLIAM SADLER , JONATHAN PEARCE , SUNGYE KIM
Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20200073664A1
公开(公告)日：2020-03-05
申请号：US16120226
申请日：2018-09-01
Applicant: Intel Corporation
Inventor： PRATIK J. ASHAR , SUPRATIM PAL , SUBRAMANIAM MAIYURAN , WEI-YU CHEN , GUEI-YUAN LUEH
Abstract: An apparatus to facilitate register sharing is disclosed. The apparatus includes one or more processors to generate first machine code having a first General Purpose Register (GRF) per thread ratio, detect an occurrence of one or more spill/fill instructions in the first machine code, and generate second machine code having a second GRF per thread ratio upon a detection of one or more spill/fill instructions in the first machine code, wherein the second GRF per thread ratio is based on a disabling of a first of a plurality of hardware threads
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公开(公告)号：US20160350112A1
公开(公告)日：2016-12-01
申请号：US14726349
申请日：2015-05-29
Applicant: Intel Corporation
Inventor： SUPRATIM PAL , SUBRAMANIAM MAIYURAN , MARK C. DAVIS
CPC classification number: G06F15/82 , G06F9/30141 , G06F9/345 , G06F9/3824 , G06F9/3851 , G06F9/3887
Abstract: Techniques to suppress redundant reads to register addresses and to replicate read data are disclosed. The redundant reads are suppressed when multiple source operands specify the same register address to read. Additionally, the read data is replicated to a data stream or data location corresponding to the source operands where the data read was suppressed.
Abstract translation: 公开了抑制冗余读取以注册地址和复制读取数据的技术。 当多个源操作数指定要读取的相同寄存器地址时，冗余读取被抑制。 此外，读取的数据被复制到对应于数据读取被抑制的源操作数的数据流或数据位置。
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公开(公告)号：US20220156343A1
公开(公告)日：2022-05-19
申请号：US17527882
申请日：2021-11-16
Applicant: Intel Corporation
Inventor： SUBRAMANIAM MAIYURAN , JORGE PARRA , SUPRATIM PAL , ASHUTOSH GARG , SHUBRA MARWAHA , CHANDRA GURRAM , DARIN STARKEY , DURGESH BORKAR , VARGHESE GEORGE
Abstract: Described herein is an accelerator device including a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a systolic array with feedback inputs.
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