公开(公告)号：US20220102259A1

公开(公告)日：2022-03-31

申请号：US17033392

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48

Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

公开(公告)号：US10672693B2

公开(公告)日：2020-06-02

申请号：US15944728

申请日：2018-04-03

Applicant: INTEL CORPORATION

Inventor： Sanka Ganesan ,  William James Lambert ,  Zhichao Zhang ,  Sri Chaitra Jyotsna Chavali ,  Stephen Andrew Smith ,  Michael James Hill ,  Zhenguo Jiang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H05K1/18 ,  H01L25/10 ,  H01L25/065 ,  H05K7/02 ,  H01L21/56

Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

公开(公告)号：US20190304887A1

公开(公告)日：2019-10-03

申请号：US15944728

申请日：2018-04-03

Applicant: INTEL CORPORATION

Inventor： Sanka Ganesan ,  William James Lambert ,  Zhichao Zhang ,  Sri Chaitra Jyotsna Chavali ,  Stephen Andrew Smith ,  Michael James Hill ,  Zhenguo Jiang

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H05K7/02 ,  H05K1/18

Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

公开(公告)号：US09953959B1

公开(公告)日：2018-04-24

申请号：US15463523

申请日：2017-03-20

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Robert Alan May ,  Yikang Deng ,  Amruthavalli Pallavi Alur ,  Sheng Li ,  Chong Zhang ,  Sri Chaitra Jyotsna Chavali ,  Amanda E. Schuckman

IPC: H01L23/02 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/4817 ,  H01L21/486 ,  H01L25/50 ,  H01L2225/0652 ,  H01L2225/06548

Abstract: A metal protected fan-out cavity enables assembly of a package-on-package (PoP) integrated circuit while reducing PoP solder spacing and overall z-height. A horizontal fan-out conductor provides a contact between a die contact and a lower package via. A metal protection layer may be used during manufacture to protect the fan-out conductor, such as providing a laser stop during laser skiving. The metal protection layer materials and an etching solution may be selected to allow for subsequent removal via etching while leaving the fan-out conductor intact. The metal protection layer and fan-out conductor materials may also be selected to reduce or eliminate formation of an intermetallic compound (IMC) between the metal protection layer and the fan-out conductor.

公开(公告)号：US12132015B2

公开(公告)日：2024-10-29

申请号：US16665682

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Sri Chaitra Jyotsna Chavali

IPC: H01L23/64 ,  H01F27/28 ,  H01F27/32 ,  H01F41/04 ,  H01F41/12 ,  H01L21/48 ,  H01L23/00 ,  H01L23/49 ,  H01L23/498

CPC classification number: H01L23/645 ,  H01F27/2804 ,  H01F27/327 ,  H01F41/041 ,  H01F41/127 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01F2027/2809 ,  H01L2224/16225 ,  H01L2924/1427 ,  H01L2924/18161 ,  H01L2924/19103

Abstract: Embodiments include inductors and methods to form the inductors. An inductor includes a substrate layer that surrounds a magnetic layer, where the magnetic layer is embedded between the substrate layer. The inductor also includes a dielectric layer that surrounds the substrate and magnetic layers, where the dielectric layer fully embeds the substrate and magnetic layers. The inductor further includes a first conductive layer over the dielectric layer, a second conductive layer below the dielectric layer, and a plurality of plated-through-hole (PTH) vias in the dielectric and substrate layers. The PTH vias vertically extend from the first conductive layer to the second conductive layer, and the magnetic layer in between the PTH vias. The magnetic layer may have a thickness that is substantially equal to a thickness of the substrate layer, where the thickness of the magnetic layer is less than a thickness defined between the first and second conductive layers.

公开(公告)号：US20240063544A1

公开(公告)日：2024-02-22

申请号：US18498411

申请日：2023-10-31

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Robert L. Sankman ,  Shawna M. Liff ,  Sri Chaitra Jyotsna Chavali ,  William J. Lambert ,  Zhichao Zhang

IPC: H01Q9/04 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/66

CPC classification number: H01Q9/0414 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6677

Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.

公开(公告)号：US11869842B2

公开(公告)日：2024-01-09

申请号：US16521435

申请日：2019-07-24

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Robert L. Sankman ,  Arghya Sain ,  Sri Chaitra Jyotsna Chavali ,  Lijiang Wang ,  Cemil Geyik

IPC: H01L23/538 ,  H01L23/498

CPC classification number: H01L23/5381 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.

公开(公告)号：US20220059367A1

公开(公告)日：2022-02-24

申请号：US17521406

申请日：2021-11-08

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Schuckman

IPC: H01L21/48 ,  H01L23/498

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

公开(公告)号：US11195727B2

公开(公告)日：2021-12-07

申请号：US16901172

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Schuckman

IPC: H01L21/48 ,  H01L23/498

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

公开(公告)号：US10903137B2

公开(公告)日：2021-01-26

申请号：US16540177

申请日：2019-08-14

Applicant: Intel Corporation

Inventor： Siddharth K. Alur ,  Sri Chaitra Jyotsna Chavali

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/373 ,  H01L23/498 ,  H01L21/48 ,  H01L23/367

Abstract: According to various embodiments of the present disclosure, an electrically conductive pillar having a substrate is disclosed. The electrically conductive pillar can comprise a first portion, second portion and a third portion. The first portion and/or third portion can be formed of an electrically conductive material that can be the same or different. The second portion can be intermediate and abut both the first portion and the third portion. The second portion can comprise a solder element formed of a second electrically conductive material that differs from the electrically conductive material and has a second stiffness less than a stiffness of the electrically conductive material.