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公开(公告)号：US20240397628A1
公开(公告)日：2024-11-28
申请号：US18797211
申请日：2024-08-07
Applicant: Intel Corporation
Inventor： Landon HANKS , Douglas HEYMANN , Xiang LI , Ariadna HERNANDEZ VAZQUEZ
Abstract: Apparatus and methods for conductive memory module notch and connector-to-motherboard pins for power or ground. A memory module includes a conductive notch that is coupled to either one or more ground planes in respective layers in the memory module's PCB or to a power rail formed on one or more layers in the PCB. A memory module connector includes a notch pin that is configured to mate with the conductive notch when the memory module is installed in the connector. The connector is mounted to a motherboard or the like and the notch pin is coupled to either power (e.g., Vin) or ground in the motherboard. When coupled to power, Vin is supplied to the memory module via the notch pin/conductive notch. When coupled to ground on the motherboard, at least a portion of the ground planes in the PCB are coupled to ground via the notch pin/conductive notch.
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公开(公告)号：US20240364037A1
公开(公告)日：2024-10-31
申请号：US18768742
申请日：2024-07-10
Applicant: Intel Corporation
Inventor： Landon HANKS , Douglas HEYMANN , John R. DREW , Xiang LI
IPC: H01R13/24
CPC classification number: H01R13/2478
Abstract: Compression Attached Memory Module (CAMM) connector pin with multi-spring (dual bend direction) levers and associated connectors. The connector pin comprises an upper cantilevered spring member coupled to an upper portion of a body and a lower cantilevered spring member coupled to a lower portion of the body. Each of the upper and lower cantilevered spring members include at least one forward bending lever and a backward bending lever. The upper cantilevered spring member may have a pair of arms merging to form an upper unified spring member having a nose and looping backwards over the arms and having an apex. A lower cantilevered spring may have a pair of legs merging to form a lower unified spring member having a nose and looping backwards under the legs and having a bottom. When compressed the forward and backward bending levers counteract one another in the horizontal plane, reducing horizontal displacement.
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公开(公告)号：US20240080988A1
公开(公告)日：2024-03-07
申请号：US18506951
申请日：2023-11-10
Applicant: Intel Corporation
Inventor： Todd A. HINCK , Michael T. CROCKER , Xiang LI , Vijaya K. BODDU
CPC classification number: H05K1/181 , H05K1/0209 , H05K7/1429 , H05K2201/10159 , H05K2201/10378
Abstract: A system includes a processor, such as a CPU, surrounded by high-density memory with lower profile than a standard DIMM. The low profile, high-density memory provides multiple memory channels for the processor. With the memory configuration, the system can maintain the memory configurability with increased density and increased memory channels for the processor.
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公开(公告)号：US20230006374A1
公开(公告)日：2023-01-05
申请号：US17899379
申请日：2022-08-30
Applicant: Intel Corporation
Inventor： Min Suet LIM , Luis Carlos ALVAREZ MATA , Ankita TIWARI , Xiang LI , Jun LIAO
Abstract: A system connects a board to a substrate through an interposer board having compressible connectors through the interposer board. The connectors through the interposer board are compression-based connector pins that extends above and below the interposer board to make electrical contact between the board and the substrate. The system can include a plate to secure the board to the substrate and compress the compression-based connectors of the interposer board.
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15.发明申请公开(公告)号：US20230005882A1
公开(公告)日：2023-01-05
申请号：US17902740
申请日：2022-09-02
Applicant: Intel Corporation
Inventor： George VERGIS , Min Suet LIM , Luis Carlos ALVAREZ MATA , Ankita TIWARI , Xiang LI
Abstract: Memory on Package (MOP) apparatus with reverse CAMM (Compression Attached Memory Module) and compression mount technology (CMT) connector(s). The MOP includes a first (MOP) substrate to which one or more CPUs, SoC, and XPUs that is operatively coupled to one or more CAMMs with a CMT connector(s) disposed between an array of CMT contact pads on the CAMM substrate and an array of CMT contact pad on the substrate. The one or more CAMMs are include multiple memory chips or packages such as LP DDR chips or DDR (S)DRAM chips/packages mounted to an underside of the CAMM substrate via signal coupling means such as a ball grid array (BGA), where the CAMM orientation is inverted such that the memory chips/packages are disposed downward, resulting in a reduced Z-height of the MOP. A MOP may include two CAMMs with a respective CMT connector disposed between the CAMM substrates and the MOP substrate.
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Patent Agency Ranking
公开(公告)号：US20220361328A1
公开(公告)日：2022-11-10
申请号：US17871686
申请日：2022-07-22
Applicant: Intel Corporation
Inventor： Xiang LI , Konika GANGULY , Tongyan ZHAI , George VERGIS , Anthony M. CONSTANTINE , Jun LIAO
Abstract: Power conversion modules using compression mount technology (CMT) connectors and associated apparatus and methods. Assemblies include a CMT connector that includes an array of spring-loaded CMT pins or contacts that are configured to contact respective pads on a pair of printed circuit board (PCBs), such as for VR module card or power conversion module and a motherboard. The power conversion modules in combination with the CMT connectors provide several advantages, including, a common VR module/power conversion module/motherboard footprint across OEM platforms and test hardware, just in time VR module attachment for improved inventory management, removable power delivery solution makes the platform more conducive to debug, in field servicing, and platform upgradable for higher power CPU/GPU/XPU.
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公开(公告)号：US20210183410A1
公开(公告)日：2021-06-17
申请号：US17132504
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Xiang LI , George VERGIS , Konika GANGULY
IPC: G11C5/04 , G11C5/06 , H01L23/00 , H01L23/538
Abstract: An apparatus is described. The apparatus includes a module to plug-into a printed circuit board. The module has a connector along a center axis of the module. The module further has a first semiconductor chip disposed in a first region of the module that resides between an edge of the module and a side of the connector. The module has a second semiconductor chip disposed in a second region of the module that resides between an opposite edge of the module and an opposite side of the connector.
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公开(公告)号：US20190102331A1
公开(公告)日：2019-04-04
申请号：US15719742
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Xiang LI , Yunhui CHU , Jun LIAO , George VERGIS , James A. McCALL , Charles C. PHARES , Konika GANGULY , Qin LI
CPC classification number: G06F13/1694 , G06F1/185 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/10 , H01R12/73
Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.
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公开(公告)号：US20230070411A1
公开(公告)日：2023-03-09
申请号：US17987382
申请日：2022-11-15
Applicant: Intel Corporation
Inventor： Min LIU , Xiang LI , Shijie LIU , Yannan SUN , Lei ZHU
IPC: G06F3/06 , G06F12/0815
Abstract: Examples described herein relate to a central processing unit (CPU) that includes at least two cores, at least two caching agents (CAs), and circuitry to monitor a workload mapped to a CA of the at least two CAs and adjust the workload allocated to the CA to allocation among the CA and at least one other CA of the at least two CAs based on the monitored workload.
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公开(公告)号：US20230007775A1
公开(公告)日：2023-01-05
申请号：US17871542
申请日：2022-07-22
Applicant: Intel Corporation
Inventor： Xiang LI , Konika GANGULY , Tongyan ZHAI , George VERGIS , Anthony M. CONSTANTINE , Jun LIAO
Abstract: Methods and apparatus for GDDR (Graphics Double Date Rate) memory expander using compression mount technology (CMT) connectors. A CMT connector with a dedicated pinout for GDDR-based memory is provided that enables end users and manufacturers to change the amount of GDDR memory provided with a GPU card, accelerator card, or apparatus having other form factors. Memory could also be replaced in the event of a failure. In addition, embodiments are disclosed that support a split channel concept where there could be multiple devices (e.g., GDDR modules) with dedicated signals routed to each module.
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