公开(公告)号：US20180039429A1

公开(公告)日：2018-02-08

申请号：US15228729

申请日：2016-08-04

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Yi ZOU ,  Jawad B. KHAN ,  Xin GUO

IPC: G06F3/06 ,  G06F12/1009 ,  G11C11/56

CPC classification number: G06F3/0616 ,  G06F3/0644 ,  G06F3/0688 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/7201 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: Provided are an apparatus, method, and system for programming a multi-cell storage cell group. A non-volatile memory has storage cells. Each storage cell is programmed with information using a plurality of threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller is configured to program the storage cells and to organize the storage cells in the non-volatile memory into storage cell groups. Each storage cell group stores a number of bits of information and each of the storage cells in each of the storage cell groups is programmed with the plurality of threshold voltage levels. The memory controller selects bits from the pages to write for one storage cell group and determines at least one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected bits in the storage cell group.

公开(公告)号：US20180004410A1

公开(公告)日：2018-01-04

申请号：US15197617

申请日：2016-06-29

Applicant: INTEL CORPORATION

Inventor： Aliasgar S. MADRASWALA ,  Yogesh B. WAKCHAURE ,  David B. CARLTON ,  Xin GUO ,  Ryan J. NORTON

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688

Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.

公开(公告)号：US20150095736A1

公开(公告)日：2015-04-02

申请号：US14040554

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Lark-Hoon LEEM ,  Xin GUO ,  Ravi H. MOTWANI ,  Rosanna YEE ,  Scott E. NELSON

IPC: G06F11/10

CPC classification number: G06F11/141 ,  G06F11/1012

Abstract: Provided are an apparatus, system, and method for performing an error recovery operation with respect to a read of a block of memory cells in a storage device. A current iteration of a decoding operation is performed by applying at least one reference voltage for the current iteration to a block of the memory cells in the storage device to determine current read values in response to applying the reference voltage. A symbol is generated for each of the read memory cells by combining the determined current read value with at least one value saved during the previous iteration. The symbols are used to determine bit reliability metrics for the block of memory cells. The bit reliability metrics are decoded. In response to the decoding failing, an additional iteration of the decoding operation is performed.

Abstract translation: 提供了一种用于对存储装置中的存储单元块的读取执行错误恢复操作的装置，系统和方法。 通过对当前迭代中的至少一个参考电压施加到存储装置中的存储器单元的块来执行解码操作的当前迭代，以响应于施加参考电压来确定当前读取值。 通过将确定的当前读取值与在先前迭代中保存的至少一个值组合，为每个读取的存储器单元生成符号。 这些符号用于确定存储器单元块的位可靠性度量。 比特可靠性度量被解码。 响应于解码失败，执行解码操作的附加迭代。

公开(公告)号：US20190043556A1

公开(公告)日：2019-02-07

申请号：US16147446

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Mark Anthony GOLEZ ,  David J. PELSTER ,  Xin GUO ,  Paul D. RUBY

IPC: G11C11/406 ,  G11C8/12

CPC classification number: G11C11/40611 ,  G11C8/12 ,  G11C11/40603 ,  G11C11/40618 ,  G11C13/0023 ,  G11C13/0033 ,  G11C13/0061 ,  G11C16/08 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/349 ,  G11C2211/4063

Abstract: A refreshing method is described. The method includes recognizing a set of blocks of a non-volatile memory for refreshing and then refreshing a subset of the data within the blocks, where, invalid data within the blocks is not recognized for refreshing and a group of blocks whose oldest data has not aged for a pre-set time period is not recognized for refreshing.

公开(公告)号：US20170285991A1

公开(公告)日：2017-10-05

申请号：US15087071

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Aliasgar S. MADRASWALA ,  Xin GUO ,  Joel T. JORGENSEN

IPC: G06F3/06

CPC classification number: G06F3/0626 ,  G06F3/0607 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688

Abstract: A solid state drive includes a controller with a hardware interface to fewer planes of memory cells than included in the nonvolatile storage. For example, a controller hardware interface can include a 1N plane interface coupled to a nonvolatile storage device with 2N planes of memory cells. For data access transactions between the controller and the nonvolatile storage device, first and second consecutive 1N plane command sequences are interpreted as a single 2N plane command sequence.

公开(公告)号：US20160379715A1

公开(公告)日：2016-12-29

申请号：US14752817

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： David J. PELSTER ,  Yogesh B. WAKCHAURE ,  Xin GUO ,  Paul D. RUBY ,  Justin R. DAYACAP ,  Joseph F. DOLLER ,  Robert E. FRICKEY

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2216/20

Abstract: Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.

Abstract translation: 提供了一种用于对非易失性存储器执行块擦除操作的装置，存储器控制器和方法。 产生用于执行块擦除操作的一部分的命令。 在执行命令后至少执行一次读或写操作。 响应于在执行至少一个读或写操作之后确定块擦除操作未完成，执行命令的附加实例。