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    Transistor device with variously conformal gate dielectric layers
    11.
    发明授权
    Transistor device with variously conformal gate dielectric layers 有权

    公开(公告)号：US11616130B2

    公开(公告)日：2023-03-28

    申请号：US16363632

    申请日：2019-03-25

    Applicant: Intel Corporation

    Inventor： Seung Hoon Sung ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Uygar Avci ,  Devin Merrill ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Owen Loh

    IPC: H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

    Abstract: Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.

    Spin orbit torque memory devices and methods of fabrication
    14.
    发明授权
    Spin orbit torque memory devices and methods of fabrication 有权

    公开(公告)号：US11574666B2

    公开(公告)日：2023-02-07

    申请号：US16246362

    申请日：2019-01-11

    Applicant: Intel Corporation

    Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Chia-Ching Lin ,  Kaan Oguz ,  Ian Young

    IPC: G11C11/16 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22

    Abstract: A memory device includes a spin orbit electrode structure having a dielectric structure including a first sidewall, a second sidewall opposite to the first sidewall, a top surface. The spin orbit electrode structure further includes an electrode having a spin orbit material adjacent to the dielectric structure, where the electrode has a first electrode portion on the top surface, a second electrode portion adjacent to the first sidewall and a third electrode portion adjacent to the second sidewall. The first electrode portion, the second electrode portion and the third electrode portion are contiguous. The spin orbit electrode structure further includes a conductive interconnect in contact with the second electrode portion or the third electrode portion. The memory device further includes a magnetic junction device on a portion of the top surface of the first electrode portion.

    Magnetostrictive stack and corresponding bit-cell
    19.
    发明授权
    Magnetostrictive stack and corresponding bit-cell 有权

    公开(公告)号：US10998495B2

    公开(公告)日：2021-05-04

    申请号：US16329721

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

    IPC: H01L43/10 ,  H01L41/187 ,  H01L41/193 ,  H01L41/20 ,  G11C11/16 ,  H01L41/00 ,  H01L27/22 ,  H01L43/08 ,  H01F10/32 ,  H01L43/02 ,  H01F10/12

    Abstract: An apparatus is provided which comprises: a ferromagnetic (FM) region with magnetostrictive (MS) property; a piezo-electric (PZe) region adjacent to the FM region; and a magnetoelectric region adjacent to the FM region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; and a magnetoelectric region, wherein the FM region is at least partially adjacent to the magnetoelectric region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; a magnetoelectric region being adjacent to the FM and PZe regions; a first electrode adjacent to the FM and PZe regions; a second electrode adjacent to the magnetoelectric region; a spin orbit coupling (SOC) region adjacent to the magnetoelectric region; and a third electrode adjacent to the SOC region.

    Magneto-electric spin orbit (MESO) structures having functional oxide vias
    20.
    发明授权
    Magneto-electric spin orbit (MESO) structures having functional oxide vias 有权

    公开(公告)号：US10957844B2

    公开(公告)日：2021-03-23

    申请号：US16346872

    申请日：2016-12-23

    Applicant: Intel Corporation

    Inventor： Jasmeet S. Chawla ,  Sasikanth Manipatruni ,  Robert L. Bristol ,  Chia-Ching Lin ,  Dmitri E. Nikonov ,  Ian A. Young

    IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L43/00 ,  H03K19/18

    Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.

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