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    ZrOx/STO/ZrOx Based Selector Element
    11.
    发明申请
    ZrOx/STO/ZrOx Based Selector Element 审中-公开
    基于ZrOx / STO / ZrOx的选择元件

    公开(公告)号：US20150179934A1

    公开(公告)日：2015-06-25

    申请号：US14136465

    申请日：2013-12-20

    Applicant: Intermolecular, Inc.

    Inventor： Monica Sawkar Mathur ,  Venkat Ananthan ,  Prashant B. Phatak

    IPC: H01L45/00

    CPC classification number: H01L27/2418 ,  H01L27/2463 ,  H01L45/00 ,  H01L45/08

    Abstract: Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on multilayer dielectric stacks. The control element can include a zirconium oxide-strontium-titanium oxide-zirconium oxide multilayer stack. The zirconium oxide can be replaced by at least one of hafnium oxide, aluminum oxide, magnesium oxide, or one of the lanthanide oxides.

    Abstract translation: 公开了可适用于非易失性存储器件应用的控制元件。 控制元件可以在低电压下具有低漏电流，以减少非选定器件的潜行电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 控制元件可以基于多层介质堆叠。 控制元件可以包括氧化锆 - 锶 - 氧化钛 - 氧化锆多层堆叠。 氧化锆可以由氧化铪，氧化铝，氧化镁或镧系元素氧化物中的至少一种代替。

    Current selector for non-volatile memory in a cross bar array based on defect and band engineering metal-dielectric-metal stacks
    14.
    发明授权
    Current selector for non-volatile memory in a cross bar array based on defect and band engineering metal-dielectric-metal stacks 有权
    基于缺陷和带工程金属 - 电介质金属叠层的交叉条阵列中的非易失性存储器的当前选择器

    公开(公告)号：US08766234B1

    公开(公告)日：2014-07-01

    申请号：US13728860

    申请日：2012-12-27

    Applicant: Intermolecular, Inc.

    Inventor： Imran Hashim ,  Venkat Ananthan ,  Tony P. Chiang ,  Prashant B. Phatak

    IPC: H01L47/00 ,  H01L45/00

    CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L29/872 ,  H01L45/10

    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

    Abstract translation: 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件开关期间的电压降。 在一些实施例中，选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括夹在两个较低的漏电介质层之间的高泄漏电介质层。 低泄漏层可以起到限制低电压下选择器装置的电流的作用。 高泄漏电介质层可以用于在高电压下增强选择器装置上的电流。

    Mimcaps with quantum wells as selector elements for crossbar memory arrays
    16.
    发明申请
    Mimcaps with quantum wells as selector elements for crossbar memory arrays 审中-公开
    量子阱的Mimcaps作为横向存储器阵列的选择器元件

    公开(公告)号：US20150137062A1

    公开(公告)日：2015-05-21

    申请号：US14560031

    申请日：2014-12-04

    Applicant: Intermolecular Inc.

    Inventor： Venkat Ananthan ,  Prashant B Phatak

    IPC: H01L27/24 ,  H01L49/02

    CPC classification number: H01L27/2418 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/76 ,  G11C2213/77 ,  H01L21/324 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/00 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Selector devices suitable for memory arrays have low leakage currents at low voltages, reducing sneak current paths for non-selected devices, and high leakage currents at high voltages, reducing voltage drops during switching. The selector device may include a non-conductive tri-layer between two electrodes. The non-conductive tri-layer may include a low-bandgap dielectric layer between two higher-bandgap dielectric layers. The high-bandgap dielectric layers may be doped to form traps at energy levels higher than the write voltage of the memory device. With a thin low-bandgap layer and a large bandgap difference from the high-bandgap layers, the selector may operate as a quantum well, conductive when the electrode Fermi level matches the lowest energy level of the quantum well and insulating at lower voltages.

    Abstract translation: 适用于存储器阵列的选择器件在低电压下具有低漏电流，减少非选定器件的潜行电流路径，以及高电压下的高泄漏电流，从而减少开关期间的电压降。 选择器装置可以包括两个电极之间的非导电三层。 非导电三层可以包括两个较高带隙电介质层之间的低带隙电介质层。 可以掺杂高带隙电介质层以在高于存储器件的写入电压的能级形成陷阱。 具有薄的低带隙层和与高带隙层的大带隙差异，当电极费米能级与量子阱的最低能级匹配并在较低电压下绝缘时，选择器可以作为量子阱进行导电。

    CURRENT SELECTOR FOR NON-VOLATILE MEMORY IN A CROSS BAR ARRAY BASED ON DEFECT AND BAND ENGINEERING METAL-DIELECTRIC-METAL STACKS
    19.
    发明申请
    CURRENT SELECTOR FOR NON-VOLATILE MEMORY IN A CROSS BAR ARRAY BASED ON DEFECT AND BAND ENGINEERING METAL-DIELECTRIC-METAL STACKS 有权
    基于缺陷和带工程金属电介质堆叠的跨栏阵列中非易失性存储器的当前选择器

    公开(公告)号：US20140183439A1

    公开(公告)日：2014-07-03

    申请号：US13728860

    申请日：2012-12-27

    Applicant: INTERMOLECULAR, INC.

    Inventor： Imran Hashim ,  Venkat Ananthan ,  Tony P. Chiang ,  Prashant B. Phatak

    IPC: H01L29/872 ,  H01L29/66 ,  H01L27/24

    CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L29/872 ,  H01L45/10

    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

    Abstract translation: 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 在一些实施例中，选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括夹在两个较低的漏电介质层之间的高泄漏电介质层。 低泄漏层可以起到限制低电压下选择器装置的电流的作用。 高泄漏电介质层可以用于在高电压下增强选择器装置上的电流。

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